Exploring three unconventional reset techniques for the 80C51

The existing reset logic in the standard 80C51 chip is relatively simple, and can only be expanded externally through a reset pin RST. The technical manual provides the wiring method of the power-on reset (POR) and manual reset (MRST) circuits; there are also articles introducing the expansion of the undervoltage reset (LVR) and watchdog reset (WDR) with the help of a dedicated peripheral chip, such as MAX813L or DS1323.

This article will introduce three unconventional extended reset methods: software reset (SWR), software and hardware reset (SHR) and illegal address reset (IAR).

Software trap technology and its improvement method

Software trap is a programming method to catch a program "runaway". Usually, a software trap can be set in the program to guide the microcontroller with a runaway program to jump to a specified address for execution, and finally return to the normal track. The software trap can be set in the gap of the user program or after the transfer instruction, and a series of trap instructions can be used to fill the blank area of ​​the program memory. The instruction to implement the software trap function is a "5-byte instruction string", which usually contains 2 single-byte NOP instructions and 1 3-byte jump instruction.

NOP; use no operation instruction

NOP; to increase capture effectiveness

LJMP SWRST; jump to the specified address unconditionally

Among them, "SWRST" can be the entry address label of a "software reset program" or the reset vector "0000H", that is, the main program entry address.
If SWRST is equal to the reset vector 0000H, the captured runaway program will be directed to the initialization program entry address for execution, thereby achieving the purpose of returning to the normal track. This processing method is only suitable for occasions where the interrupt function is not enabled. It can be imagined that if the program runs away in the (low-level or high-level) interrupt service program, even if the program is pulled back to the starting point, the interrupt activation trigger cannot be cleared, which will affect the subsequent interrupt requests and cannot be responded to by the CPU.

If SWRST is equal to the entry address of the "software reset program", a "software reset" will be triggered. The design method of the software reset program will be introduced later.

In short, the guiding principle of this method is to fill the unused ROM space with jump guide instructions as a software "trap" to capture the "flying" program, and forcibly guide the captured runaway program to a specific address, where it is processed by a special program for handling errors to restore the normal operation of the system. In order to improve the capture rate of the runaway program, it is usually necessary to place several no-operation instructions NOP before the guide instruction. The reason is that the instruction encoding of 8051 adopts unequal length, with a length of 1 to 3 bytes, and the program runaway is formed by illegally changing the PC value randomly. If the PC value after the runaway falls in the middle of the 3-byte instruction LJMP, the operand will be executed as an opcode, which will produce unpredictable results. In order to improve the effectiveness of the capture, at least 2 single-byte NOP instructions are filled before the LJMP instruction.

If the "5-byte instruction string" is replaced with the "4-byte instruction string" newly designed by the author as follows, the trap instruction will be more effective. The reason is that the target code corresponding to the instruction is "00 20 00 20H", and this code is equivalent no matter how many times it is repeated. In addition, a transfer instruction LJMP SWRST that jumps to the real entrance of the "software reset program" should be placed in the 3 bytes starting from 0020H of the program memory. After verification, the bytes 0020H to 0022H are exactly located at the end of the timer T1 interrupt vector area and before the serial port interrupt vector.

SWRST0 EQU 0020H; define the indirect entry address of "software reset program" as "0020H"
NOP; fill a single-byte no operation instruction, the machine code is "00H"
LJMP SWRST0; unconditionally jump to the specified address. The corresponding machine code is "20 00 20H"

Software reset technology

Software reset is a new technology, and more and more new MCUs are equipped with this function. For example, Philips' P87LPC700 and P89LPC900 series, TI-BB's MSC1200 series, and SunPlus's SPMC65 series all have control registers or control bits designed specifically for software reset.

Software reset is a necessary follow-up processing task when using software trap technology or software watchdog technology. The so-called "software reset" is a reset activity controlled by user software, which uses a series of instructions to simulate the various operations implemented by hardware reset and re-execute the user program from the beginning.

The operations should include: (1) Reset operation of the 21 special function registers (SFRs) of the standard 80C51, which can be easily achieved using the MOV instruction. It may not be necessary to reset all of them, only those SFRs used in the user program can be reset, which can be customized by the user.

2) For the reset of the program timer PC without unified addressing, a jump instruction can be used. (3) The reset of the interrupt activation trigger is easily overlooked and difficult to implement. The reason is that they are invisible to the user program and their contents cannot be directly read or written. Some programmers use LJMP 0000H (machine code is 20 00 00H) as a software trap, thinking that directly jumping to the reset vector completes the software reset. This is a typical example of this type of error case.

Why is it necessary to clear the interrupt activation trigger? The program runaway occurs randomly, and its takeoff point may occur in the low-level or high-level interrupt service subroutine, when the interrupt activation trigger has been set. If they are not cleared in time after the program resumes, all subsequent interrupt requests of the same level or lower level will be blocked.

Figure 1 Schematic diagram of interrupt activation trigger

The interrupt activation trigger contains two triggers, a high-priority group and a low-priority group. The circuit composition is shown in Figure 1, which is drawn based on the author's understanding and experience. The circuit includes a logic OR gate G1 and two SR triggers FF1 and FF2. After the CPU responds to a low-level interrupt request, FF1 is set, its Q = 0, blocking the "low-priority group" and no longer accepting new low-level interrupt requests; when the CPU responds to a high-level interrupt request, due to the effect of G1, FF1 and FF2 are set at the same time, FF1's Q = 0 blocks the "low-priority group", and FF2's Q = 0 blocks the "high-priority group", and no longer accepts new high-level and low-level interrupt requests.

How to design a "software reset program"? The writing method is as follows.

SWRST: ; Define the actual entry address of the software reset program
CLR EA ; First turn off the interrupt source enable bit
SETB F0 ; Set a software reset flag
MOV P0, #0FFH ; Set the general port P0 to high-impedance input state
MOV P1, #0FFH ; Set the general port P1 to high-impedance input state
MOV P2, #0FFH ; Set the general port P2 to high-impedance input state
MOV P3, #0FFH ; Set the general port P3 to high-impedance input state
MOV PSW, #00H ; Set the program status word register to the original value
... ; (Other SFRs can also be initialized according to actual needs)
MOV DPTR, #SWR0 ; Prepare the pop-up address for RETI, but do not want to change the execution order
PUSH DPL ; Push the low byte on the stack, first
PUSH DPH ; Push the high byte on the stack, later
RETI ; Interrupt return instruction, clear the high-level interrupt activation trigger
SWR0: CLR A ; Prepare the reset address
PUSH ACC ; Push the low byte 00H
PUSH ACC; Push high byte 00H
RETI; Clear low-level interrupt activation trigger and jump to 0000H

The following points need to be explained: (1) First, turn off the general interrupt enable bit to ensure that the software reset process is completed smoothly; (2) The core instruction is the interrupt return instruction RETI, because only this instruction in the entire instruction set can clear the interrupt activation trigger; (3) The function of the RETI instruction at the end also replaces a 3-byte "LJMP 0000H" instruction; (4) The runaway program captured by the software trap does not necessarily set all two interrupt activation triggers at the same time, but the program is still applicable and has no negative impact; (5) The software reset flag here uses a general bit F0 in the PSW, and can also use F1, GF0, GF1, and RAM byte units or bit units; (6) Software reset is a pure software reset method that does not expand any hardware circuits and does not cause the microcontroller to transition state.

Software and hardware reset technology

The software and hardware reset is an extension of the software reset function, and is also an autonomous reset method for the microcontroller. It has the characteristics of both software reset (which can be enabled by the programmer as needed) and hardware reset (which can implement all the operations of hardware reset). This reset method was planned, designed, and named by the author of this article.

(a) Discrete circuit method

(b) IC circuit method

It is easy to implement the software and hardware reset method mentioned here on the basis of the above software reset, but it requires the support of certain hardware circuits. Figure 2 shows two external expansion circuits for software and hardware reset. Among them, the circuit in Figure 2 (a) is based on the ordinary reset circuit, adding a transistor Q1 and three resistors and capacitors, and its conduction and cutoff are controlled by a parallel port pin, such as P1.0. Usually P1.0 maintains a high level and Q1 is cut off; when the internal software needs to implement the reset, a low level is output from the P1.0 pin, Q1 is turned on to pull the RST pin high, and the microcontroller is reset forcibly. Here R3, R4 and C2 play a dual role of delay and current limiting. The circuit in Figure 2 (b) is based on the MAX812M docking 80C51 circuit and adds a connection line. Its working principle is similar to the above. This connection line connects the manual reset input pin MR of the MAX812M and a general I/O pin (such as P1.0).

How to design a "software and hardware reset program"? The writing method is as follows.

SHRST: ; Define the entry address of the software and hardware reset program
SET F1 ; Set a software reset flag
CLR P1.0 ; Output low level from P1.0 to start the software and hardware reset
ORL PCON, #02H; Set PD to make the MCU enter the shutdown state, that is, PD mode
; After a delay, RST is pulled high, forcing the MCU to enter the reset state
; After the reset operation is completed and the MCU is awakened, the user program will be executed again from 0000H
The following points need to be explained: (1) If the "software and hardware reset program" here is used instead of the previous "software reset program", the user program can be simplified and the reset can be carried out thoroughly, but some hardware needs to be added, and the customizable reset operation is also converted into a fixed reset operation. (2) In addition to providing a reset signal to the MCU, the software and hardware reset support circuit shown in Figure 2 has a great advantage, that is, it can provide a reset signal to other peripheral circuits, which makes up for a deficiency of the traditional 80C51.

The reset pin RST of the standard 80C51 is a unidirectional structure that can only be input, and the microcontroller cannot actively provide a synchronous reset signal for peripheral chips; while the MC68HC05 and MC68HC08 series, ST's ST7 series, and many new 51-compatible microcontrollers all design the RST pin as a bidirectional structure that can be input/output. When the internal watchdog overflows and resets, a high-level pulse is also output from RST to control other peripheral chips to perform synchronous reset operations with the microcontroller. For example, ATMEL's AT89S51/52, T89C51RD2, AT89C51RC and other models and Philips' P89C51RC, P89C51RA2/RB2/RD2 and other models all have internal watchdogs.

Illegal address reset technology

Generally speaking, an illegal address reset means that the contents of the program timer PC are destroyed due to unexpected reasons, forcing the CPU to try to fetch instruction code to execute at an illegal address, thus forcing the microcontroller to perform a reset operation.

Since the hardware structure of the 51 series MCU adopts the "Harvard architecture", its program area and data area are completely separated and independently addressed, and there is no possibility of the CPU fetching instructions from the RAM area, so this greatly reduces the probability of illegal addressing. However, this cannot completely eliminate the possibility of illegal addressing, especially for those situations where the actual ROM capacity is far less than 64Kb. At this time, the illegal address can be narrowly defined as the address code where the PC value exceeds the actual ROM capacity.

(a) IC circuit direct reset method

(b) Interrupt first and then reset

Figure 3 shows two support circuits for implementing illegal address reset. Among them, the circuit in Figure 3 (a) is formed by changing a line based on Figure 2 (b). One end of the line is connected to the PSEN signal pin, which is specifically used to provide a chip select signal for selecting the external program memory ROM; the other end is connected to the manual reset input pin MR of MAX812M. Normally, the PSEN pin is always maintained at a high level; only when the CPU attempts to illegally fetch instructions from the external ROM, the PSEN pin will send a low-level pulse, which cleverly uses the pulse as a reset signal source to force the microcontroller to perform a reset operation. The circuit in Figure 3 (b) can be regarded as a change based on Figure 2 (b) by adding a line. The line connects the PSEN signal pin and an external interrupt source pin INT0, and sets INT0 as a falling edge trigger and a high-level interrupt source. When an illegal address appears, the low-level pulse on the PSEN pin requests an interrupt to the CPU through INT0; after the CPU responds to the interrupt, a flag can be set, and then a software reset or a software and hardware reset can be implemented.

One thing needs to be pointed out: there are prerequisites for enabling the illegal address reset mode. It is only applicable to those situations where the on-chip ROM (referring to the program memory) is purely utilized, that is, there is no external ROM, and the on-chip ROM is less than 64Kb.

Summary of reset methods

The standard 80C51 has only one external reset source pin RST. Basically all hardware interrupts are introduced through the RST pin, and are expanded one by one according to actual needs. Among them, only the power-on reset POR is indispensable in any occasion. Its expansion order roughly conforms to (not absolutely conforms to) the rules in Table 1.

Here, the various reset sources and reset methods that may be used are classified into the following different categories.

1 Traditional reset method and non-traditional reset method

Traditional reset methods (including power-on reset and manual reset) are mentioned in almost all 80C51 technical manuals and textbooks; while non-traditional reset methods (including undervoltage reset, watchdog reset, software reset, software and hardware reset, and illegal address reset) are expanded to meet the needs of technological development. These are also some of the new microcontrollers that have newly added reset methods on the chip.

2 Hardware reset, software reset and hardware and software reset

The reset classification is shown in Table 2. All reset modes except software reset are externally introduced to the RST reset pin.

3 Power supply voltage monitoring reset and program operation monitoring reset

The power supply voltage monitoring reset includes power-on reset and undervoltage reset, both of which are resets implemented during abnormal periods of power supply voltage; the program operation monitoring reset includes manual reset, watchdog reset, illegal address reset, software reset and hardware and software reset, both of which are resets implemented when the user program malfunctions.

4 Internal reset and external reset

Internal reset includes watchdog reset, software reset, hardware and software reset and illegal address reset, which are basically resets caused by internal reasons; external reset includes power-on reset, manual reset and undervoltage reset, which are basically resets caused by external reasons.

5 Fast reset and delayed reset

The former hopes that the reset operation is as fast as possible, such as manual reset, watchdog reset, illegal address reset, etc.; while the latter hopes that the reset operation has a delay time, such as power-on reset, undervoltage reset, etc.

6 Cold Reset and Warm Reset

Only the power-on reset is a cold reset, and the rest are warm resets. Before the cold reset is implemented, the microcontroller is in a power-off state.