PIC16C84 is an 8- bit CMOS EEPROM microcontroller. It has high-performance RISC -like instructions, with a total of 35 single-byte instructions. All instructions require only one instruction cycle, except for program branch instructions, which require two instruction cycles. When the main oscillation frequency is 10MHZ , one instruction cycle is 400ns . The width of the program instruction is 14 bits, and there is a 1K×14 EEPROM program memory in the chip .
The data width is 8 bits. There are 36×8 static RAM general registers and 64×8 EEPROM data memory in the chip . 8 -level deep hard stack. Direct, indirect and relative addressing modes. There are 4 interrupt sources: external RBO / INT pin; TMRO timer overflow, change of signal on PORTB < 7 : 4 > pin; data writing to EEPROM completed.
The data memory can be erased/written up to 1,000,000 times, and the data can be retained for more than 40 years. There are 13 -bit I / O pins that can be directly controlled individually. Each I / O pin can withstand an input/output current of 25mA , so that the LED can be driven directly . There is an 8- bit timer/counter ( TMRO ) with an 8 -bit programmable prescaler. There are power-on reset ( POR ); power rise ( POWER - UP ) timer ( PWRT ); oscillator start timer ( OST ); watchdog timer ( WDT ). In order to work reliably , it has its own RC oscillator. There is a code guarantee function. There is a SLEEP mode to save power consumption. There are 4 oscillators to choose from: RC (low-cost RC oscillator); XT (standard crystal/resonator); HS (high-speed crystal / resonator); LP ( low- power , low- frequency crystal). The operating voltage range is wide from 2.0V to 6.0V .
The biggest feature of the PIC16C84 microcontroller is that it has a 1K×14- bit electrically erasable program memory and a 64×8- bit electrically erasable data memory, which will provide more convenience for system development and various applications.
Clock and instruction cycle
The clock input from OSCI is divided by 4 internally . Non-superimposed clock cycles are generated. Every 4 clock cycles (θ 1 , θ 2 , θ 3 , θ 4 ) constitute an instruction cycle. Each θ 1 is added by 1 in the internal program counter , and then the instruction is fetched from the program memory. The fetched instruction is placed in the instruction register at θ 4. The instruction is executed during the next θ 1 and θ 4. The instruction fetching and execution of instructions adopt pipeline technology. Instructions are fetched in one instruction cycle, and the fetched instruction is executed in the next instruction cycle, and the next instruction is fetched at the same time. Therefore, the CPU time for each instruction execution is one instruction cycle. When an instruction needs to change the content of the program counter (such as a branch instruction), it takes two instruction cycles to complete. The fetched instruction is placed in the instruction register at θ 1 of the execution instruction cycle, and the instruction is decoded and executed at θ 2 , θ 3 , and θ 4. The operand is read during θ 2 and written during θ 4 .
Memory structure
There are two memory blocks in the PIC16C84 microcontroller. That is, the program memory and the data memory. Each block has its own bus, which means that each block can be accessed in the same clock cycle. The data memory is further divided into general RAM and special function registers ( SFRs ). The special function registers are used to control the peripheral mode. The data memory also contains the data EEPROM memory . This memory is not directly mapped to the data memory, but indirectly mapped. That is, an indirect addressing pointer indicates the address of the data EEPROM to be read/written . The 64 -byte data EEPROM has addresses from 0 to 3FH .
3-1 Program Memory Structure
PIC16C84 microcontroller has a 13 -bit program counter and an addressing capacity of 8K×14- bit program memory space. In fact, only 1K×14 -bit program memory (address 0000 ~ 03FFH ) is available for PIC16C84 . If the address exceeds the above address range, the address will wrap around. For example, the 20H unit and the addresses 420H , 820H , C20H , 1020H , 1420H , 1820H , 1C20H will all access it. When the system is reset, the PC value is 0000H and the interrupt vector is 0004H .
PC ＜ 12 ： 0 ＞
CALL ， RETURN 13
RETFIE , RETLW 1st level stack
．
8- level stack
Reset address 0000H
External interrupt vector 0004H
User storage space 3FFH
1FFFH
Figure 4-2 Program storage image and stack
3-2 Data memory structure
The data memory is divided into two areas. The first is the special function register ( SFR ) area, and the second is the general purpose register area ( GPR ). SFR controls the operation of the device. The data memory is divided into block 0 and block 1. Block 0 ( RP1 = 0 , RP0 = 0 ) or block 1 ( RP0 = 1 ) is selected by setting the RP1 : RP0 bits in the status register STATUS during the program .
The part with slashes is a unit that does not actually exist, and the unit with an asterisk is not physically stored. The instructions MOVWF and MOVF can transfer the value of the W register ( the W register is the working register inside the device ) to any unit in the register file (" F" ), and vice versa. The entire data memory can be directly addressed or indirectly addressed through the file select register ( FSR ). Indirect addressing depends on the status of the RP1 : RP0 bits of the status register to determine which block of the data memory The two blocks of the data memory are divided into general registers and special registers. Each low-address unit is reserved for special registers, and the units are general registers, which are static RAM .
1. General register file The register file can be addressed directly or indirectly through FSR . All devices have a certain number of general registers ( GPR ), and their data width is 8 bits. PIC16C84 has only 36 bytes of general registers, with addresses 0CH to 2FH . Access to a block of 8CH to AFH will actually access 0CH to 2FH (the high bits of the address are ignored).
The CPU and peripherals use special registers to control the operation of the device. Special registers are static RAM . Here are some important special registers
① Status register
The status register contains the arithmetic status of the ALU (ALU), the reset status and the block selection for the data memory. Like any register, the status register can be used as the destination register for any instruction. If the status register is used as the destination register for an instruction , and that instruction affects the status of the Z , DC , and C bits, writing these three bits is prohibited. Figure 4-4 shows the status register and its status .
R ／ WR ／ WR ／ WRRR ／ WR ／ WR ／ W
IRP RP1 RP0 TO PD Z DC C bit7 bit0
Where C is the carry bit. For ADDWF and ADDLW instructions, when this bit is 1 , it indicates that the most significant bit of the result of the instruction operation has a carry output. The subtraction instruction executes the new code of the second operand. For the loop instruction ( RRF , RLF ), this bit can come from the high bit or the low bit of the source register. If this bit is 0 , it indicates that the most significant bit of the result has not produced a carry output. For subtraction, the polarity of this bit is inverted. DC is the digital carry or digital borrow bit. When this bit is 1 , there is a carry from D3 to D4 of the result , otherwise there is no carry. For subtraction, the polarity of this bit is inverted. Z is the result 0 flag. When this bit is 1 , it indicates that the result of arithmetic and logical operations is 0 , otherwise this bit is 0 , indicating that the result of the operation is not 0. PD : Low power bit. When this bit is 1 , it indicates that the power is added to the normal power supply or after the C LRWDT instruction is executed , this bit is 0 to indicate that the SLEEP instruction is executed (that is, the device enters a low power state). TO timeout bit. When this bit is 1 , it indicates that the power is on, the normal power supply has been entered, and the CLRWDT and SLEEP instructions have been executed . This bit is 0 , indicating that the watchdog timer has timed out.
RP1 : RP0 , as the block select bit for directly addressed data memory.
Each block is 128 bytes. PIC16C84 only uses RP0 bit, and RP1 is set to 0 when programming . It is not allowed to use RP1 as a general read/write bit, which may affect compatibility with future products. IRP register block selection bit (as indirect addressing). When this bit is set to 0 , select 0.1 blocks (address 00H ~ FFH ), and when this bit is 1 , select 2.3 blocks (address 100H ~ 1FFH ). PIC16C84 does not use IRP bit, and IRP bit is 0 when programming . Z , DC , C bits in the status register are set or cleared according to the logic of the device . TO and PD bits are not writable. The result of the instruction with the status register as the destination register will have different contents. For example, CLRF STATUS (clear the status register). The content of the resulting status register is 000uuluu . Among them, u means no change. Only the BCF , BSF , SWAPF and MOVW F instructions can be used to change the contents of the STATUS register because these instructions do not affect any status bits.
② OPTION register
The OPTION register is a readable and writable register that contains various control bits to configure the TMRO / WDT prescaler, external INT interrupt, TMRO and the weak pull-up on PORTB . Figure 4-5 shows the functions of each bit in the OPTION register. R / WR / WR / WR / WR / WR / WR / WR / WR / WR
RBPU INTEDG TOCS TOSE PSA PS2 PS1 PS0 bit7 bit0
PS2 , PS1 , PS0 are the prescaler value selections. (Same as the PIC16C6X ). The PSA bit is used to assign the prescaler to the WDT (watchdog timer, or TMR0 ).
TOSE is the transition signal for TMRO
INTEDG is used to select the transition signal for the INT interrupt pin.
RBPU is used to turn on or off the internal pull-up resistor of PORTB .
The definition of all OPTION bits is the same as that of the PIC16C6X series.
③ INTCON register
INTCON is a readable and writable register that contains the interrupt source to enable or disable interrupts . Figure 4-6 is the INTCON register of PIC16C84
R ／ WR ／ WR ／ WR ／ WR ／ WR ／ WR ／ WR ／ W
GIE EEIE TOIE INTE RBIF TOIF INTIF RB IF bit7 bit0
RBIF is the RB port change interrupt flag. When this bit is 1 , it indicates that at least one bit in the RB < 7 : 4 > input has changed. It must be cleared to 0 by software . Otherwise, it is 0 , that is, there is no change in the RB < 7 : 4 > input. INTIF is the external interrupt flag. When this bit is 1 , it indicates that an external interrupt has occurred . It must be cleared to 0 by software . Otherwise, it is 0 , indicating that no external interrupt has occurred.
TOIF is the TMRO overflow interrupt flag. This bit is 1 , indicating that TMRO has overflowed, and must be cleared to 0 by software. Otherwise, it is 0 , indicating that TMRO has not overflowed.
RBIE is the enable or disable bit for the RB port change interrupt. Setting this bit to 1 enables the interrupt and to 0 disables it.
INTE is the enable or disable bit of the INT interrupt. Setting it to 1 enables the interrupt mode, and setting it to 0 disables it .
TOIE is the enable or disable bit for TMRO overflow interrupt. Set it to 1 to enable TMRO overflow interrupt, otherwise disable it.
EEIE is the enable and disable bit of EE (Electrically Erasable) write completion interrupt. When set to 1 , EE write completion interrupt is allowed, otherwise it is disabled.
GIE is the enable and disable of all interrupts. When set to 1 , all non-maskable interrupts are enabled, and 0 is disabled.
4. PCL and PCLATH The program counter (PC) is 13 bits. The low byte PCL is a readable and writable register. The high byte of PC (PCH) is not directly readable and writable. PCLATH (PC latch high) is a holding register for PC<12:8>, and the contents of these bits are transferred to the high bits of the program counter. When the program counter executes instructions such as CALL, GOTO or write PCL, a new value is loaded into the PC. The high bits of PC are loaded by PCLATH. There are 8 13-bit wide hardware stacks. The stack space is neither part of the program memory nor a part of the data memory, and the stack pointer is not readable/writable. When a CALL instruction is executed or an interrupt is responded to, the entire 13-bit PC is pushed into the stack. When executing instructions such as RETURN, RETLW, RETFIE, etc., the stack is popped. PUSH (push) and POP (pop) do not affect PCLATH. The stack is used as a circular buffer. When the stack is pushed 38 times, the 9th push will take the place of the first push, the 10th push will take the place of the second push, and so on. Similarly, when the stack is popped for the 9th time, it is the same as the first pop. Note that there are no status bits to indicate stack overflow or underflow conditions. There are no PUSH or POP instruction mnemonics, but the execution of CALL, R ETURN, RETLW, RETFIE, etc. instructions or the occurrence of an interrupt will actually push and pop the stack. 4-2 Pages of Program Memory The PIC16C84 has 1K of program memory. The CALL and GOTO instructions only have an 11-bit address range. This 11-bit address range allows branches within the 2K program memory page size range. For future expansion of the PIC16C8X program memory, two more bits must be used to specify the program memory page. These page bits come from PCLATH<4:3>. When executing CALL and GOTO instructions, the user must ensure that the programming of these page bits points to the required program memory page. If a CALL instruction is executed, the entire 13 bits are pushed onto the stack. Therefore, the management of PCLATH<4:3> bits is not required for return instructions. Because the value of PC will be obtained by popping the stack. Note: PIC16C84 ignores PCLATH<4:3> bits, which are used for program storage pages 1, 2, and 3 (0800H-1FFFH). The PCLATH<4:3> bits of PIC16C84 cannot be used as general read/write bits, which will affect the upward compatibility of future products. 4-3 Indirect addressing, the role of INDF and FSR The INDF register is not a physical register, but is used to connect with the FSR register to perform indirect addressing. Using the INDF register, indirect addressing can be achieved. For any instruction using the INDF register, the actual addressing data is determined by the file select register (FSR). Reading INDF itself (FSR=0) will produce 00H. Writing to INDF results in no operation (obviously, it can provide status bits). The 8-bit FSR register is combined with the status register STATUS<7> (IRP) to obtain a 9-bit address. However, PIC16C84 does not use IRP. Use the following example program to clear by indirect addressing. 2OH~2FH units. MOVLW 20H; Initialize the RAM pointer MOVF FSR; To FSR NEXT CLRF INDF; Clear by indirect addressing, the register pointed to by the content of FSR. INCF FSR; (FSR) + 1 → FSR BIFSS FSR, 4; When the 4th bit of FSR is 1, skip the next instruction GOTO NEXT; Otherwise enter. Five I/O ports PIC16C84 has two I/O ports, PORTA and PORTB. Some port pins are used to multiplex with other functions. 5-1 PORTA and TRISA register PIC16C84's PORTH is a 5-bit wide latch. RA4 is a Schmitt trigger input and an open collector output. All other pins of port A are TTL level inputs with CMOS output drivers. All pins have a data direction bit (TRISA register), and the pins of PORTA can be configured as input outputs through TRISA. If a bit of TRISA is set to 1, the corresponding bit of PORTA is input. If it is set to 0, the corresponding bit of PORTA is output. Read the PORTA register to read the pin status. Write to PORTA and write to the latch of PORTA. All write operations are read-modify-write operations. When writing to a port, it first reads the port pin, then modifies its bit, and then writes to the port data latch. The following program is to initialize port A: CLRF PORTA; initialize port A BSF STATUS, RPO; select 1 block MovLW CFH; used to initialize the value of data direction MOVWF TRISA; set RA<3:0> as input; RA<5:4> as output; <7:6> is always 0 (unused) RA4 is multiplexed for the clock input of TMRO. That is, if this bit is used as the clock input of TMRO, port A cannot use RA4. 5-2 PROTB and TRISB registers PORTB is a bidirectional port with a width of 8 bits. The corresponding data is determined by TRISB, and the method uses port A. Each pin of port B has an internal weak pull-up resistor. All pull-up resistors can be turned on by a control bit. This can be controlled by setting 1 and clearing 0 to OPTION<7> RBPU bit. When the port pin is configured as an output, the internal weak pull-up resistor is automatically turned off. The upper bit is required by the port. The four pins RBT~RB4 of PORTB have the function of signal change interrupt. As long as these pins are configured as inputs, an interrupt may occur. In input mode, the pin bit is compared with the value of the last read PORTB. If any one or more of these four pins are different, the RBIF bit is generated (set INTCON<0>). This interrupt may wake up the device from the SLEEP state. The user can clear the interrupt in one of the two ways in the interrupt service routine. ① Turn off the interrupt by clearing 0RBIE (INT CON<3> bit), ② Read port B, then clear 0 RBIF bit. Unequal conditions will continue to configure 1RBIF bit. Reading PORTB will end the inequality condition and allow RBIF to be cleared. This feature, together with the software configurable pull-up, allows the user to easily use PORTB as a keyboard input interface. This also allows the system to be woken up by a key press. Note: If a I/O pin changes a signal while a key press is in progress, the RBIF interrupt flag cannot be set to 1. It is recommended to use the change signal interrupt as a key wake-up operation. PORTB does not need to use the change signal interrupt. It is not recommended to use the query mode. Figure 4-7 is a schematic diagram of using the port as a keyboard interface. R1 is a newly selected resistor for ESD protection. When using this interface, the internal pull-up is kept high through software selection, that is, RB4~RB7 is set to input mode. RB0~RB3 output. When any key is pressed, one of the lines of RB4~RB7 will change to generate an interrupt. This interrupt can wake up the chip, and timer resources can be saved in this way. 16 keys RB4 100 RB5 RB6 RB7 RB0 RB1 RB2 BR3 Rf Figure 4-7 Keyboard interface diagram using port B. 5-3 Considerations of I/O Programming Any write operation to a port is internally read-modify-write. For example, the BCF and BSF instructions first read the register into the CPU, perform the bit operation, and write the result back to the register. For example, to perform a BSF operation on PORTB, first read the 8 bits of PORTB into the CPU, perform the BSF operation on Bit5, set this bit to 1, and write PORTB back to the output latch. If bit0 of PORTB is used as an input pin at this time, PORTB is first read into the CPU, then the relevant operation is performed, and the result is written back to the latch of PORTB, overwriting the previous content. If bit0 has always remained in input mode, this operation is no problem, but if bit0 is changed to output mode after being pinned, the content of the data latch is unknown. The actual writing of an I/O port occurs at the end of an instruction cycle, while the valid data of a read of an I/O port must appear at the beginning of the instruction cycle. Therefore, when performing read and write operations on an I/O channel, the reliability of the data must be considered. To this end, a NOP instruction should be added between these two instructions to ensure the reliability of the data. 6. Timer (TMRO) modeTMRO timer/counter mode has the following features: ·8-bit timer counter·Readable, writable·8-bit software programmable prescaler·Overflow interrupt from FFH to 00H·Edge selection of external clock The simple block diagram of TMRO mode is the same as that of PIC16C6X series. It can select the timer mode by clearing the TOCS bit (i.e. OPTION<5>). In the timer mode, TMRO mode adds 1 for each instruction cycle (no prescaler). If TMRO is written, the timer is incremented (the operation is disabled for the last two cycles). TOCS is 1 (OPTION<5>) to select TMRO as counter mode. In this mode, TMRO will add 1 for the up or down transition on the RA4/TOCK1 pin. Clearing TOSE (OPTION<4>) selects the up transition, otherwise it is the down transition. The use of the prescaler is the same as that of PIC16C6X series. When the value of TMRO changes from FFH to 00H in the timer/counter mode, an overflow interrupt is generated. This overflow interrupt will set the TOIF bit to 1. This interrupt can be masked by setting the TOIE bit to 0. To generate an interrupt again, TOIF must be cleared to 0 by software in the interrupt service routine. The TMRO interrupt cannot be used to wake up the chip. Because in the SLEEP state, the timer is turned off. For how to use the external clock of TMRO, the synchronization of the external clock, the use of the prescaler, etc., refer to the technical performance of TMRO in the PIC16C6X series. VII. Data EEPROM Memory The data EEPROM memory is readable and writable during normal operation at full power supply voltage (VDD). This part of the memory cannot be directly mapped to the register file space. It can only be accessed through indirect addressing through special function registers. There are four SFRs used to read and write these memories. These registers are EECON1; EECON2; EEDATA; EEDAR. Among them, EEDATA is used to hold 8-bit read/write data. EEADR is used to hold the address of the EEPROM unit being accessed. PIC16C84 has 64 bytes of EEPROM, and the address range of its unit is 00H-3FH. EEPROM allows one byte to be read/written at a time. Writing a byte will automatically erase the unit and write the new content (erased before writing). EEPROM data memory is a high-speed erase/write cycle, and the write time is normally 10ms, which is controlled by the chip's timer. The actual write time is related to the applied voltage, temperature, chip, etc. Please refer to the chip's AC specification for strict time. When the device is in code protection, only the CPU can complete the read/write of the data memory. That is, the device programmer no longer accesses the memory (external read/write is turned off). 6 Connection considerations Because the analog inputs use ESD protection, they have reverse-biased diodes connected to VDD and VSS. This requires that the analog input voltage should be between VDD and VSS. If the analog input voltage exceeds the maximum value of 0.6V, the diode may become forward-conducting, and if the input current exceeds the specification, it may damage the device. Sometimes an external RC filter is added to the input signal. The selected resistor R should ensure that the total signal source resistance does not exceed 10K, and any other additional components on the analog signal should have very small leakage current. 7. Conversion function Theoretically, the conversion function of the A/D converter is as follows. When the analog input signal voltage is the voltage of 1 bit Lsb (or VREF/256), the first conversion occurs. 8 Flowchart of A/D conversion Table 2-4 Registers involved in A/D conversion of PIC16C74/73 Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0B/8B INTCON GIE PEIE 0C PIR1 ADIF 8C PIE1 ADIE 0D PIR2 CCP2IF 8D PIE2 CCP2IE 1F ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON 9F ADCON1 PCFG2 PCFG1 PCFG0 In addition to the registers listed above, ADRES (address 1EH) is used to store the results of A/D conversion. PORTA (address 05H) is used to input multiple analog signals, TRISA (address 85H) is used to set the I/O mode of PORTA, PORTE (address 09H) is used to input multiple analog signals, and TRISE (address 89H) is used to set the I/O mode of PORTE. Table 2-5 Register address involved in A/D conversion of PIC16C71 Name bit7 bit6 bit5 bit4 bit3 bit 2 bit1 bit0 0B/8B INTCON GIE ADIE 08 AOCON0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADIF ADON 88 ADCON1 PCFG1 PCFG0 In addition, ADRES (address 09H), PORTA, TRISA, etc. are also involved. UUUUUUUUUR/PR/PR/PR/PR/PR － － － － － － － － CP PWRTE WDTE FOSC 1 FOSC0 bit 13 bit0 Figure 4-10 Configuration register of PIC16C84 7-3 Writing EEPROM data memory and writing EEPROM data unit, the user must first write the address to the EEADR register, then send the data to EEDA?TA, and finally the user must follow a special sequence to start writing. For example, the following program is for writing to the EEPROM. ? ? BSF STATUS, RPO; select 1 block BCF INTCON, GIE; disable all INT interrupts MOVLW 55H; MOVWF EECON2; write 55H MOVLW AAH; MOVWF EECON2; write AAH BSF EECON1, WR; set WR bit to 1, start writing to BSF INTCON, GIE; enable INT interrupts. If this program (i.e., write 55H to EECON2 first, then write AAH to EECON2, then set WK=1) is not followed in strict time, the write will not start. We recommend that interrupts be disabled during the execution of these instructions. In addition, the WREN bit in EECON1 must be selected to 1 to allow writing. This mechanism prevents the data EEPROM from being written due to the execution of erroneous instructions. The user should keep the WREN bit at 0 at all times, except when hot-modifying the EEPROM. After the write sequence begins, clearing the WREN bit will not affect the write cycle. From the beginning, the WR bit will be disabled until WREN = 1. When the write cycle is completed, the WR bit is cleared by hardware. The write completion interrupt flag EEIF is set to 1, and EEIF must be cleared by software. Note that the data EEPROM memory E/W cycle may occasionally exceed 10ms. To ensure the completion of the write cycle, the user uses the EE interrupt or polls the WR bit (EECON1 <1>). Both can be used to determine the completion of the write cycle. In addition to the above-mentioned prevention of erroneous writing of the data EEPROM, writing of the EEPROM data memory is also prevented within 72ms during the power-on period. Eight CPU-specific features The microcontroller is distinguished from other processors by special circuits that involve the needs of real-time applications. PIC16C84 has the greatest system reliability, the lowest price, the least external components, and provides a low-function operating mode and code protection. PIC16C84 has a watchdog timer, which can only be turned off by the configuration bit. In order to increase its reliability, its RC oscillator is turned off. There are two timers to provide the delay required at power-on. The Oscillator Start-up Timer (OST) keeps the chip in reset until the crystal is stable. The other is the Power-up Timer (PWRT), which providesFixed 72ms delay. This ensures device reset and reliable power supply. With these two timers, most applications do not require an external reset circuit. The SLEEP mode provides a low power mode. Users can wake up the chip through external reset; watchdog timer overflow; interrupt. 8-1 Configuration bits Configuration bits are divided into programmable bits, read as 0, and non-programmable bits, read as 1. Various configurations are selected through programmable bits. These bits are mapped to the 2007H unit of the program memory. Note that address 2007H is not equal to the user program memory space. In fact, it belongs to a special test/configuration storage space (2000H~3FFH) that can only be accessed during programming. Figure 4-10 is the structure of the configuration register (attached) Among them, Fosc<1 or 0> is the oscillator selection bit. 11: Select RC oscillator 10: Select HS oscillator 01: Select XT oscillator 00: Select CP oscillator WDTE is the selection bit for watchdog enable and disable. This bit is 1 to allow the watchdog to work. This bit is 0 to disable the watchdog from working. PWRTE is the selection of power-on timer enable and disable. When this bit is 1, the power-on timer is enabled, and when it is 0, it is disabled. CP is the selection of code protection. When this bit is 1, the code protection is canceled, and when this bit is 0, the code of all program memory is protected. The remaining bits are not executed. Read as 1. Regarding the configuration of the oscillator, the oscillator selection and connection circuit are the same as those of the PIC16C6X series. 8-2 Interrupts PIC16C84 has 4 interrupt sources. That is, the interrupt on the external interrupt RBO/INT pin, TMR0 overflow interrupt; PORTB change interrupt (RB7:RB4); EEPRDM write completion interrupt. The interrupt control register (INTCON) records each interrupt request in its flag bit. It also includes the enable/disable bit of each interrupt. The enable/disable bit of all interrupts (INTCON<7>) opens all interrupts or disables all interrupts. When returning from the interrupt return instruction RETFLE, the interrupt is exited and GIE=1 is set to reopen all interrupts. The interrupt flags of RBO/INT pin interrupt, RB port change interrupt and TMRO overflow interrupt are in the INTCON register. When the interrupt is responded, the GIE bit is cleared to 0, any new interrupt is closed, the return address is pushed into the stack, and the PC is loaded with 0004H. For external interrupt files, such as RBO/INT pin or PORTB change interrupts, this type of interrupt requires 3 to 4 instruction cycles. The strict time depends on the occurrence of the interrupt event. Once in the interrupt service routine, the interrupt source can be determined by querying the interrupt flag bit. The interrupt flag bit should be cleared to 0 by software before re-developing this interrupt. Note: ① The flag bit of each interrupt is set, regardless of its corresponding mask bit or GIE. ②If an interrupt occurs, and the enable bit GIE in all interrupts is assumed to be cleared to 0, GIE may be accidentally connected to 1 by the RETFIE instruction of the user interrupt service program. This may happen when a. When the interrupt is responded to, the instruction clears the GIE bit to 0. b. The program branches to the interrupt vector and executes the interrupt service program. c. The interrupt service program executes the RETFIE instruction and completes. This will cause the GIE bit to be set to 1 (enabling interrupts). At the same time, the program returns to the instruction after the interrupt is turned off (in fact, the interrupt cannot be turned off due to the above reasons). To ensure that GIE is cleared to 0, there should be the following program. l00p BGF INT CON, GIE: Turn off all interrupts BTFSC INTCON, GIE; Are all interrupt enable bits turned off? GOTO l00P; No return to l00p, then clear GIE to 0, otherwise the program continues. 1. The external interrupt on RBO/INT of INT interrupt is edge triggered. If the INT?EDG bit (OPTION ＜6＞) is set to 1, the rising edge is valid, if the INTEDG bit is cleared to 0, the falling edge is valid. When a valid jump occurs on the RBO/INT pin, the INTF bit (INTCON＜1＞) is set to 1. Clear the INTE control bit (INTCON＜4＞) to disable this interrupt. INTF should be cleared to 0 by software in the interrupt service routine before re-enabling this interrupt. Before the chip enters SLEEP, if the INTE bit is set to 1, the chip can be woken up after the INT interrupt occurs. The state of the GIE bit determines whether the processor branches to the interrupt vector after being woken up. 2. TMRO interrupt TMRO overflow (from FFH to 00H) will set the TOIF bit (INTCON＜2＞) to 1. This bit of interrupt can open/close the interrupt by setting or clearing the TOIE (INTCON＜5＞) bit. 3. PORTB interrupt When the input of port B bits 7 to 4 changes, the RBIF (INTCON＜0＞) bit is set to 1. This interrupt can be opened or closed by setting RBIE (INTCON<3>) to 1 or clearing it to 0. Note: When the RB port is being read, RB7~RB4 change, and the RBIF flag may not be set to 1. 4. How to save the W and STATUS registers during an interrupt. During an interrupt, the hardware automatically pushes the value of the PC into the stack. This is called saving the breakpoint. Users often want to save the contents of key registers (such as the W and STATUS registers). To do this, execute the following program. MOVWF W－TEMP; copy W register to W－TEMP register, W－TEMP register can be in block 1 or block 0 SWAPF STATUS, W; send status register contents to W BCF STATUS, RPO; select block 0 MOVWF STATUS－TEMP; copy status register contents (now in W STATUS－TEMP register interrupt service routine SWAPF STATUS－TEMP, W; send STATUS－TEMP to W (set block to original state) MOVWF STATUS; send W to STATUS (restore STATUS) SWAPF W－TEMP, 0; send W－TEMP to W (restore contents of W) In the above program, W－TEMP register must be defined in two blocks and at the same block base address. For example, define W－TEMP at 20H in block 0, and it should also be defined at A0H in block 1. Register STATUS－TEMP must be defined in block 0. 5. Watchdog Timer (WDT) The watchdog timer actually uses an on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator (master oscillator clock) connected to the OSC1/CLKIN pin. In this way, even if the OSC1/CLKIN and OSC2/CLKOUT pins stop oscillating (for example, after executing the SLEEP instruction), the WDT can still work. In normal operation, the output of the WDT timer generates the RESET signal of the device. If the device is in the SLEEP state, the output of the WDT timer will wake up the device and allow the device to continue to work normally. The WDT can also be turned off through programmed configuration. The block diagram of its content is the same as that of the PIC16C6X series. IX. The instruction system of the PIC16C84 microcontroller has a total of 35 instructions. It is exactly the same as the instructions of the PIC16C6X series.This is the structure of the configuration register (attached). Among them, Fosc <1 or 0> is the oscillator selection bit. 11: Select RC oscillator 10: Select HS oscillator 01: Select XT oscillator 00: Select CP oscillator WDTE is the selection bit for watchdog enable and disable. This bit is 1, allowing the watchdog to work. This bit is 0 to disable the watchdog. PWRTE is the selection for power-on timer enable and disable. This bit is 1, the power-on timer is allowed to work, and it is 0 to disable it. CP is the selection of code protection. This bit is 1 to cancel code protection. This bit is 0, and all program memory codes are protected. The remaining bits are not executed. Read as 1. Regarding the configuration of the oscillator, the selection of the oscillator and the connection circuit are the same as those of the PIC16C6X series. 8-2 Interrupts The PIC16C84 has 4 interrupt sources. That is, the interrupt on the external interrupt RBO/INT pin, TMR0 overflow interrupt; PORTB change interrupt (RB7: RB4); EEPRDM write completion interrupt. The interrupt control register (INTCON) records each interrupt request in its flag bit. It also includes the enable/disable bit of each interrupt. The enable/disable bit of all interrupts (INTCON<7>) opens all interrupts or disables all interrupts. When returning from the interrupt return instruction RETFLE, the interrupt is exited and GIE=1 is set to reopen all interrupts. The interrupt flags of RBO/INT pin interrupt, RB port change interrupt and TMRO overflow interrupt are in the INTCON register. When the interrupt is responded, the GIE bit is cleared to 0, any new interrupt is closed, the return address is pushed into the stack, and the PC is loaded with 0004H. For external interrupt files, such as RBO/INT pin or PORTB change interrupts, this type of interrupt requires 3 to 4 instruction cycles. The strict time depends on the occurrence of the interrupt event. Once in the interrupt service routine, the interrupt source can be determined by querying the interrupt flag bit. The interrupt flag bit should be cleared to 0 by software before re-developing this interrupt. Note: ① The flag bit of each interrupt is set, regardless of its corresponding mask bit or GIE. ②If an interrupt occurs, and the enable bit GIE in all interrupts is assumed to be cleared to 0, GIE may be accidentally connected to 1 by the RETFIE instruction of the user interrupt service program. This may happen when a. When the interrupt is responded to, the instruction clears the GIE bit to 0. b. The program branches to the interrupt vector and executes the interrupt service program. c. The interrupt service program executes the RETFIE instruction and completes. This will cause the GIE bit to be set to 1 (enabling interrupts). At the same time, the program returns to the instruction after the interrupt is turned off (in fact, the interrupt cannot be turned off due to the above reasons). To ensure that GIE is cleared to 0, there should be the following program. l00p BGF INT CON, GIE: Turn off all interrupts BTFSC INTCON, GIE; Are all interrupt enable bits turned off? GOTO l00P; No return to l00p, then clear GIE to 0, otherwise the program continues. 1. The external interrupt on RBO/INT of INT interrupt is edge triggered. If the INT?EDG bit (OPTION ＜6＞) is set to 1, the rising edge is valid, if the INTEDG bit is cleared to 0, the falling edge is valid. When a valid jump occurs on the RBO/INT pin, the INTF bit (INTCON＜1＞) is set to 1. Clear the INTE control bit (INTCON＜4＞) to disable this interrupt. INTF should be cleared to 0 by software in the interrupt service routine before re-enabling this interrupt. Before the chip enters SLEEP, if the INTE bit is set to 1, the chip can be woken up after the INT interrupt occurs. The state of the GIE bit determines whether the processor branches to the interrupt vector after being woken up. 2. TMRO interrupt TMRO overflow (from FFH to 00H) will set the TOIF bit (INTCON＜2＞) to 1. This bit of interrupt can open/close the interrupt by setting or clearing the TOIE (INTCON＜5＞) bit. 3. PORTB interrupt When the input of port B bits 7 to 4 changes, the RBIF (INTCON＜0＞) bit is set to 1. This interrupt can be opened or closed by setting RBIE (INTCON<3>) to 1 or clearing it to 0. Note: When the RB port is being read, RB7~RB4 change, and the RBIF flag may not be set to 1. 4. How to save the W and STATUS registers during an interrupt. During an interrupt, the hardware automatically pushes the value of the PC into the stack. This is called saving the breakpoint. Users often want to save the contents of key registers (such as the W and STATUS registers). To do this, execute the following program. MOVWF W－TEMP; copy W register to W－TEMP register, W－TEMP register can be in block 1 or block 0 SWAPF STATUS, W; send status register contents to W BCF STATUS, RPO; select block 0 MOVWF STATUS－TEMP; copy status register contents (now in W STATUS－TEMP register interrupt service routine SWAPF STATUS－TEMP, W; send STATUS－TEMP to W (set block to original state) MOVWF STATUS; send W to STATUS (restore STATUS) SWAPF W－TEMP, 0; send W－TEMP to W (restore contents of W) In the above program, W－TEMP register must be defined in two blocks and at the same block base address. For example, define W－TEMP at 20H in block 0, and it should also be defined at A0H in block 1. Register STATUS－TEMP must be defined in block 0. 5. Watchdog Timer (WDT) The watchdog timer actually uses an on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator (master oscillator clock) connected to the OSC1/CLKIN pin. In this way, even if the OSC1/CLKIN and OSC2/CLKOUT pins stop oscillating (for example, after executing the SLEEP instruction), the WDT can still work. In normal operation, the output of the WDT timer generates the RESET signal of the device. If the device is in the SLEEP state, the output of the WDT timer will wake up the device and allow the device to continue to work normally. The WDT can also be turned off through programmed configuration. The block diagram of its content is the same as that of the PIC16C6X series. IX. The instruction system of the PIC16C84 microcontroller has a total of 35 instructions. It is exactly the same as the instructions of the PIC16C6X series.This is the structure of the configuration register (attached). Among them, Fosc <1 or 0> is the oscillator selection bit. 11: Select RC oscillator 10: Select HS oscillator 01: Select XT oscillator 00: Select CP oscillator WDTE is the selection bit for watchdog enable and disable. This bit is 1, allowing the watchdog to work. This bit is 0 to disable the watchdog. PWRTE is the selection for power-on timer enable and disable. This bit is 1, the power-on timer is allowed to work, and it is 0 to disable it. CP is the selection of code protection. This bit is 1 to cancel code protection. This bit is 0, and all program memory codes are protected. The remaining bits are not executed. Read as 1. Regarding the configuration of the oscillator, the selection of the oscillator and the connection circuit are the same as those of the PIC16C6X series. 8-2 Interrupts The PIC16C84 has 4 interrupt sources. That is, the interrupt on the external interrupt RBO/INT pin, TMR0 overflow interrupt; PORTB change interrupt (RB7: RB4); EEPRDM write completion interrupt. The interrupt control register (INTCON) records each interrupt request in its flag bit. It also includes the enable/disable bit of each interrupt. The enable/disable bit of all interrupts (INTCON<7>) opens all interrupts or disables all interrupts. When returning from the interrupt return instruction RETFLE, the interrupt is exited and GIE=1 is set to reopen all interrupts. The interrupt flags of RBO/INT pin interrupt, RB port change interrupt and TMRO overflow interrupt are in the INTCON register. When the interrupt is responded, the GIE bit is cleared to 0, any new interrupt is closed, the return address is pushed into the stack, and the PC is loaded with 0004H. For external interrupt files, such as RBO/INT pin or PORTB change interrupts, this type of interrupt requires 3 to 4 instruction cycles. The strict time depends on the occurrence of the interrupt event. Once in the interrupt service routine, the interrupt source can be determined by querying the interrupt flag bit. The interrupt flag bit should be cleared to 0 by software before re-developing this interrupt. Note: ① The flag bit of each interrupt is set, regardless of its corresponding mask bit or GIE. ②If an interrupt occurs, and the enable bit GIE in all interrupts is assumed to be cleared to 0, GIE may be accidentally connected to 1 by the RETFIE instruction of the user interrupt service program. This may happen when a. When the interrupt is responded to, the instruction clears the GIE bit to 0. b. The program branches to the interrupt vector and executes the interrupt service program. c. The interrupt service program executes the RETFIE instruction and completes. This will cause the GIE bit to be set to 1 (enabling interrupts). At the same time, the program returns to the instruction after the interrupt is turned off (in fact, the interrupt cannot be turned off due to the above reasons). To ensure that GIE is cleared to 0, there should be the following program. l00p BGF INT CON, GIE: Turn off all interrupts BTFSC INTCON, GIE; Are all interrupt enable bits turned off? GOTO l00P; No return to l00p, then clear GIE to 0, otherwise the program continues. 1. The external interrupt on RBO/INT of INT interrupt is edge triggered. If the INT?EDG bit (OPTION ＜6＞) is set to 1, the rising edge is valid, if the INTEDG bit is cleared to 0, the falling edge is valid. When a valid jump occurs on the RBO/INT pin, the INTF bit (INTCON＜1＞) is set to 1. Clear the INTE control bit (INTCON＜4＞) to disable this interrupt. INTF should be cleared to 0 by software in the interrupt service routine before re-enabling this interrupt. Before the chip enters SLEEP, if the INTE bit is set to 1, the chip can be woken up after the INT interrupt occurs. The state of the GIE bit determines whether the processor branches to the interrupt vector after being woken up. 2. TMRO interrupt TMRO overflow (from FFH to 00H) will set the TOIF bit (INTCON＜2＞) to 1. This bit of interrupt can open/close the interrupt by setting or clearing the TOIE (INTCON＜5＞) bit. 3. PORTB interrupt When the input of port B bits 7 to 4 changes, the RBIF (INTCON＜0＞) bit is set to 1. This interrupt can be opened or closed by setting RBIE (INTCON<3>) to 1 or clearing it to 0. Note: When the RB port is being read, RB7~RB4 change, and the RBIF flag may not be set to 1. 4. How to save the W and STATUS registers during an interrupt. During an interrupt, the hardware automatically pushes the value of the PC into the stack. This is called saving the breakpoint. Users often want to save the contents of key registers (such as the W and STATUS registers). To do this, execute the following program. MOVWF W－TEMP; copy W register to W－TEMP register, W－TEMP register can be in block 1 or block 0 SWAPF STATUS, W; send status register contents to W BCF STATUS, RPO; select block 0 MOVWF STATUS－TEMP; copy status register contents (now in W STATUS－TEMP register interrupt service routine SWAPF STATUS－TEMP, W; send STATUS－TEMP to W (set block to original state) MOVWF STATUS; send W to STATUS (restore STATUS) SWAPF W－TEMP, 0; send W－TEMP to W (restore contents of W) In the above program, W－TEMP register must be defined in two blocks and at the same block base address. For example, define W－TEMP at 20H in block 0, and it should also be defined at A0H in block 1. Register STATUS－TEMP must be defined in block 0. 5. Watchdog Timer (WDT) The watchdog timer actually uses an on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator (master oscillator clock) connected to the OSC1/CLKIN pin. In this way, even if the OSC1/CLKIN and OSC2/CLKOUT pins stop oscillating (for example, after executing the SLEEP instruction), the WDT can still work. In normal operation, the output of the WDT timer generates the RESET signal of the device. If the device is in the SLEEP state, the output of the WDT timer will wake up the device and allow the device to continue to work normally. The WDT can also be turned off through programmed configuration. The block diagram of its content is the same as that of the PIC16C6X series. IX. The instruction system of the PIC16C84 microcontroller has a total of 35 instructions. It is exactly the same as the instructions of the PIC16C6X series.l00P; does not return to l00p, then clear GIE, otherwise the program continues. 1. INT interrupt The external interrupt on RBO/INT is edge triggered. If the INT?EDG bit (OPTION <6>) is set to 1, the rising edge is valid, if the INTEDG bit is cleared to 0, the falling edge is valid. When a valid jump occurs on the RBO/INT pin, the INTF bit (INTCON <1>) is set to 1. Clear the INTE control bit (INTCON <4>) to turn off this interrupt. INTF should be cleared to 0 by software in the interrupt service routine before re-enabling this interrupt. Before the chip enters SLEEP, if the INTE bit is set to 1, the chip can be woken up after the INT interrupt occurs. The state of the GIE bit determines whether the processor branches to the interrupt vector after being woken up. 2. TMRO interrupt TMRO overflow (from FFH to 00H) will set the TOIF bit (INTCON <2>) to 1. This bit of interrupt can open/close the interrupt by setting the TOIE (INTCON <5>) bit to 1 or clearing it to 0. 3. PORTB interrupt When the input of port B bits 7 to 4 changes, the RBIF (INTCON <0>) bit is set to 1. This interrupt can be opened or closed by setting the RBIE (INTCON <3>) bit to 1 or clearing it to 0. Note: When the RB port is being read, RB7 to RB4 change, and the RBIF flag may not be set to 1. 4. How to save the W and STATUS registers during an interrupt. During an interrupt, the hardware automatically pushes the value of the PC into the stack. This is called saving the breakpoint. Users often want to save the contents of key registers (such as the W and STATUS registers). To do this, execute the following program. MOVWF W－TEMP; copy W register to W－TEMP register, W－TEMP register can be in block 1 or block 0 SWAPF STATUS, W; send status register contents to W BCF STATUS, RPO; select block 0 MOVWF STATUS－TEMP; copy status register contents (now in W STATUS－TEMP register interrupt service routine SWAPF STATUS－TEMP, W; send STATUS－TEMP to W (set block to original state) MOVWF STATUS; send W to STATUS (restore STATUS) SWAPF W－TEMP, 0; send W－TEMP to W (restore contents of W) In the above program, W－TEMP register must be defined in two blocks and at the same block base address. For example, define W－TEMP at 20H in block 0, and it should also be defined at A0H in block 1. Register STATUS－TEMP must be defined in block 0. 5. Watchdog Timer (WDT) The watchdog timer actually uses an on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator (master oscillator clock) connected to the OSC1/CLKIN pin. In this way, even if the OSC1/CLKIN and OSC2/CLKOUT pins stop oscillating (for example, after executing the SLEEP instruction), the WDT can still work. In normal operation, the output of the WDT timer generates the RESET signal of the device. If the device is in the SLEEP state, the output of the WDT timer will wake up the device and allow the device to continue to work normally. The WDT can also be turned off through programmed configuration. The block diagram of its content is the same as that of the PIC16C6X series. IX. The instruction system of the PIC16C84 microcontroller has a total of 35 instructions. It is exactly the same as the instructions of the PIC16C6X series.l00P; does not return to l00p, then clear GIE, otherwise the program continues. 1. INT interrupt The external interrupt on RBO/INT is edge triggered. If the INT?EDG bit (OPTION <6>) is set to 1, the rising edge is valid, if the INTEDG bit is cleared to 0, the falling edge is valid. When a valid jump occurs on the RBO/INT pin, the INTF bit (INTCON <1>) is set to 1. Clear the INTE control bit (INTCON <4>) to turn off this interrupt. INTF should be cleared to 0 by software in the interrupt service routine before re-enabling this interrupt. Before the chip enters SLEEP, if the INTE bit is set to 1, the chip can be woken up after the INT interrupt occurs. The state of the GIE bit determines whether the processor branches to the interrupt vector after being woken up. 2. TMRO interrupt TMRO overflow (from FFH to 00H) will set the TOIF bit (INTCON <2>) to 1. This bit of interrupt can open/close the interrupt by setting the TOIE (INTCON <5>) bit to 1 or clearing it to 0. 3. PORTB interrupt When the input of port B bits 7 to 4 changes, the RBIF (INTCON <0>) bit is set to 1. This interrupt can be opened or closed by setting the RBIE (INTCON <3>) bit to 1 or clearing it to 0. Note: When the RB port is being read, RB7 to RB4 change, and the RBIF flag may not be set to 1. 4. How to save the W and STATUS registers during an interrupt. During an interrupt, the hardware automatically pushes the value of the PC into the stack. This is called saving the breakpoint. Users often want to save the contents of key registers (such as the W and STATUS registers). To do this, execute the following program. MOVWF W－TEMP; copy W register to W－TEMP register, W－TEMP register can be in block 1 or block 0 SWAPF STATUS, W; send status register contents to W BCF STATUS, RPO; select block 0 MOVWF STATUS－TEMP; copy status register contents (now in W STATUS－TEMP register interrupt service routine SWAPF STATUS－TEMP, W; send STATUS－TEMP to W (set block to original state) MOVWF STATUS; send W to STATUS (restore STATUS) SWAPF W－TEMP, 0; send W－TEMP to W (restore contents of W) In the above program, W－TEMP register must be defined in two blocks and at the same block base address. For example, define W－TEMP at 20H in block 0, and it should also be defined at A0H in block 1. Register STATUS－TEMP must be defined in block 0. 5. Watchdog Timer (WDT) The watchdog timer actually uses an on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator (master oscillator clock) connected to the OSC1/CLKIN pin. In this way, even if the OSC1/CLKIN and OSC2/CLKOUT pins stop oscillating (for example, after executing the SLEEP instruction), the WDT can still work. In normal operation, the output of the WDT timer generates the RESET signal of the device. If the device is in the SLEEP state, the output of the WDT timer will wake up the device and allow the device to continue to work normally. The WDT can also be turned off through programmed configuration. The block diagram of its content is the same as that of the PIC16C6X series. IX. The instruction system of the PIC16C84 microcontroller has a total of 35 instructions. It is exactly the same as the instructions of the PIC16C6X series.
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