Monostable delay circuit composed of single op amp

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Monostable delay circuit composed of single op amp [Copy link]

Monostable delay circuit composed of single op amp

Author: Unknown Source: Unknown Added Date: 2005-1-7 2618

　The monostable delay circuit is composed of a single operational amplifier connected as a voltage comparator. The circuit is shown in the attached figure. It has the characteristics of simple circuit and convenient delay adjustment.
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　　In normal state, the IC output maintains a low level, and this state is stable. When a negative pulse is input to the inverting end through C1, the potential of the inverting end is lower than the potential of the non-inverting end, and the output end flips from a low level to a high level. This state is unstable. This high level is added to the non-inverting end of the IC after voltage division by R1 and R2, so that the potential of the non-inverting end is higher than that of the inverting end, thereby maintaining a high level output. At the same time, the high level is charged through R3 and C2. When the voltage on C2 is charged to make the potential of the inverting end higher than the potential of the non-inverting end, its output end flips to a low level again. . At this time, the potential of the in-phase terminal is approximately zero, and the voltage on C2 is rapidly discharged to the output terminal through VD1, accelerating the circuit to return to its initial state. After the circuit stabilizes, the potential of the inverting terminal is still higher than the potential of the in-phase terminal, so that the output low level can be maintained.
　　The delay time T of this circuit depends not only on R3 and C2, but also on the voltage divider ratio of R1 and R2. Therefore, it is very convenient to adjust the delay time. You can adjust C2 and R3 for coarse delay adjustment, and adjust R2 for fine adjustment (if the voltage divider ratio is 1/2 to 2/3, the delay accuracy is higher). However, this circuit The state of the circuit when it is powered on is random. There are two ways to make the circuit have a unique output state after powering on: one is to add R4 to the circuit. In this way, when powered on, since the voltage on C1 cannot change suddenly, the power supply voltage is added to the inverting terminal through R4 and C1, and the output can be set to a low level; the other is to connect a diode VD2 and a switch S between the inverting terminal and the ground (as shown by the dotted line). When powered on, if the output is high, although this state is unstable, as mentioned above, it will take time T for the output to be low, and in practice, the circuit often needs Reset immediately when powered on. To this end, S can be turned on first when powered on. If the output is high, C2 can be charged to 0.7V to reset the circuit, greatly shortening the time for power-on reset of the circuit. After resetting, S is disconnected and the circuit can work normally.
　　In practical applications, if R1 is 100kΩ and R2 is 200kΩ, the voltage division ratio is 2/3, and the trigger delay time is about 0.7R3×C2. C1 can be 0.1μF and R3 can be more than 10kΩ. IC can use single-power op amps or comparators, such as LM324 or LM339.