[AG32VF407 Review] A Preliminary Study on FPGA Engineering

lenxvp

[AG32VF407 Review] A Preliminary Study on FPGA Engineering [Copy link]

 

After all, AG32VF407 is a combination of MCU+FPGA, so we still have to play with FPGA.

Refer to the software development process section in MANUAL_AGRV2K.pdf , first open the official LED Demo , unzip it to your own project directory, and open the Supra software, which is in the directory where the SDK is unzipped.

In Supra, go to File->Open Project in the menu bar and select the file with the .proj suffix in the directory where the LED Demo we downloaded above was unzipped.

Then Tool->Migrate, the parameters can be modified according to MANUAL_AGRV2K.pdf , no changes are made here, just go to next

Use Quartus to open the led.qpf project file under LED_Demo. In the Quartus menu bar, go to Tool->Tcl Scripts, select af_quartus.tcl, and then click Run. Wait for the file to complete.

Compile in Quartus

After the compilation is completed, you also need to compile in Supra. In Supra, go to Tool->Compile. No need to modify anything, just RUN

After the compilation is complete, you can download it to the development board. In Supra, go to Tool->Program, select JLink, and then Query device ID. The Device ID is 0x40200001

After downloading, you can see the LED flashing on the development board

Finally, take a look at the code and process of LED_Demo

module led(clk,ledout);
	input	clk;
	//input	rst;
	//output en;
	output [3:0] ledout;

	reg [3:0]  ledout;
	reg [31:0] counter;
	wire c0;

	always@(posedge c0)
	begin
		counter <= counter+1;
		case(counter[26:24])
			0:	ledout <= 4'b1110;
			1:	ledout <= 4'b1101;
			2:	ledout <= 4'b1011;
			3:	ledout <= 4'b0111;
			4:	ledout <= 4'b1100;
			5:	ledout <= 4'b0011;
			6:	ledout <= 4'b0000;
			7:	ledout <= 4'b1111;
		endcase
	end
	
	pll1	pll1_inst(
		.areset(1'b0),
		.inclk0(clk),
		.c0 (c0)
	);
endmodule

Verilog language is used in FPGA development. The above code generates a clock count signal through the PLL module and assigns a value to the LED according to the highest bit of the count value.

Different from the general FPGA development process, the development of AG32VF407 FPGA does not require the configuration of pin constraints in Quartus, but in the ve file. In this way, the ve file looks like the pin constraint file of AG32VF407.

lenxvp

You can download the latest version of Quartus from Intel's official website. I use version 22.1. There are multiple versions of Quartus. If you only need the Cyclone IV series for development, you can choose the free lite version.

火辣西米秀

The official website's Quartus-lite-22.1std.1.917 is the latest version

freebsder

Thanks for sharing, looking forward to the follow-up!

hexiaoyan_1024

Thanks for sharing!

Beijing Taisu Technology's " 6U VPX signal processing card based on DSP TMS320C6678+FPGA XC7V690T" is really good!