Reading check-in stop 4: A comprehensive look at chip design -- "The Great Chip"

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Reading check-in stop 4: A comprehensive look at chip design -- "The Great Chip" [Copy link]

Event details: Get to know "The Amazing Chip"

This is the fourth stop of the "Amazing Chip" reading card. Please reply to the author and ask the following questions. The author Wen Ge will help you with the reading card questions:

1. Briefly describe the front-end to back-end process of chip design.
2. What is the goal of clock tree synthesis?
3. What technologies are involved in EDA research and development?
4. How many stages can the life cycle (lifespan) of a chip be divided into? Which stage has the lowest probability of failure?
5. In Convolutional Neural Networks (CNN), what is the concept of padding? What are its types?
6. In chip design, what is a pipeline? Can the number of pipeline stages be increased indefinitely? What factors will limit the number of pipeline stages?

Friends who are reading together this time, check in at the fourth stop, follow up:

@media学子
@eew_V04Cyi
@lux168
@青天qintian0303
@qinyunti
@luke7
@lll00214
@ddllxxrr
@zhangjsh
@陈鲁隆

qinyunti

1.Briefly describe the process from front-end to back-end of chip design.

Front-end: architecture definition, RTL design, functional verification (pre-simulation), logic synthesis, formal verification, design for testability

Backend: layout planning and layout, clock tree synthesis, routing, parasitic parameter extraction, functional verification (post-simulation), physical verification of layout
2. What is the goal of clock tree synthesis?

Reducing clock delay and effectively utilizing clock offset may control China offset within a certain range.
3. What technologies are involved in EDA research and development?

Microelectronics, computer science, graphics, algorithms, computational mathematics, topological logic, artificial intelligence, etc.
4. How many stages can the life cycle (lifespan) of a chip be divided into? Which stage has the lowest probability of failure?

Early failure period, accidental failure period, and loss failure period. Accidental failure period has the lowest failure probability.
5. In convolutional neural networks (CNN), what is the concept of padding? What are the types of padding?

Padding refers to filling pixels around the original image to avoid the image becoming smaller after the convolution operation and to avoid the number of convolutions of edge pixels decreasing, so as to fully extract edge features. The following are commonly used

1.0Padding

2. Constant filling

3. Mirror Fill

4. Repeat filling

6. In chip design, what is a pipeline? Can the number of pipeline stages be increased indefinitely? What factors will limit the number of pipeline stages?

Pipelining is the process of breaking down the computer instruction processing process into multiple steps and speeding up execution by executing them in parallel through multiple hardware processing units.

Cannot be infinitely increased

The deeper the pipeline, the higher the complexity, the greater the area overhead and the greater the power consumption.

Each stage of the pipeline requires handshake, and the back pressure signal of the last stage of the pipeline may crosstalk to the first stage and cause serious timing problems.

The deeper the pipeline, the greater the waste and loss of prediction failures

传媒学子

1.Briefly describe the process from front-end to back-end of chip design.

Market research-architecture definition-RTL design-functional simulation (pre-simulation)-logic synthesis-formal verification-design for testability-layout planning and layout-clock tree synthesis-wiring-parasitic parameter extraction-functional verification (post-simulation)-physical verification of layout-tapeoutl

2. What is the goal of clock tree synthesis?

The most important goal is to reduce clock delay, effectively utilize clock offset or control clock offset within a certain range.

3. What technologies are involved in EDA research and development?

EDA is an interdisciplinary subject that integrates microelectronics, computer science, graphics, algorithms, computational mathematics, topological logic, and artificial intelligence. The above technologies constitute the core of EDA. Algorithms are one of the most core EDA technologies.

4.How many stages can the life cycle (lifespan) of a chip be divided into? Which stage has the lowest probability of failure?

According to the bathtub curve, the service life of a chip can be divided into three stages: initial failure, intrinsic failure, and breakdown failure;

The failure rate of intrinsic failure is very low.

5. In Convolutional Neural Networks (CNN), what is the concept of padding? What are its types?

Padding is a way to fill a circle of pixels around the original pixels to adapt to the algorithm.

There are various ways to fill. You can choose different filling methods according to different scenarios, such as filling with 0, filling with constants, filling with mirrors, etc.

6. In chip design, what is a pipeline? Can the number of pipeline stages be increased indefinitely? What factors will limit the number of pipeline stages?

The so-called pipeline means that when executing instructions, each instruction is divided into multiple steps, multiple instructions are placed in the same clock cycle, and different steps are run in turn and overlapped using different parts of the same set of hardware, thereby realizing parallel processing of multiple instructions to speed up the execution process of the program.

The number of pipeline stages cannot be increased indefinitely.

Additional hardware overhead, design complexity, etc. limit the number of pipeline stages.

秦天qintian0303

1. The front end includes: architecture definition, RTL design, functional verification (pre-simulation), logic synthesis, formal verification, and testability design. The back end includes: layout planning and layout, clock tree synthesis, routing, parasitic parameter extraction, functional verification (post-simulation), and physical verification of the layout.
2. The most important goal is to reduce clock delay, effectively utilize clock offset or control clock offset within a certain range.
3. EDA integrates microelectronics, computer science, graphics, algorithms, computational mathematics, topological logic, artificial intelligence and other disciplines.
4. The service life (lifespan) of a chip can be divided into early failure period, accidental failure period, and wear failure period. The probability of failure in the accidental failure period is the lowest.
5. Padding refers to filling a circle of pixels around the original image to prevent the image from becoming smaller, and the features of the image edge can be extracted.

6. Pipelining means that when executing instructions, each instruction is divided into multiple steps, multiple instructions are placed in the same clock cycle, and different steps are run in turn and overlapped using different parts of the same set of hardware to achieve parallel processing of multiple instructions and speed up the program running process; it cannot be increased indefinitely; the main impact is hardware overhead and design complexity, etc.;

ddllxxrr

Briefly describe the process from front-end to back-end of chip design.
Digital chip front-end design --> digital chip design verification --> digital chip testability design --> digital chip back-end design.
What is the goal of clock tree synthesis?
Minimize clock delay and control clock offset within a certain range.
What technologies are involved in EDA research and development?
You must know the platform and tools, programming, and English.

How many stages can the life cycle (lifespan) of a chip be divided into? Which stage has the lowest probability of failure?
Early failure, accidental failure, and wear and tear failure. The second stage has the lowest probability of failure.

In convolutional neural networks (CNN), what is the concept of padding? What are the types? Padding
is added around the original image. It is divided into convolutional layer, pooling layer, national connection layer, and output layer.

In chip design, what is a pipeline? Can the number of pipeline stages be increased indefinitely? What factors will limit the number of pipeline stages?
Each instruction is divided into multiple steps. No. Cost and designer level.

还没吃饭

1. The process from front-end to back-end of chip design generally includes the following steps: - Front-end design: including functional specification definition, logic design, RTL design, verification, etc. - Logic synthesis: synthesize RTL design files into a netlist at the logic gate level. - Physical design: including layout design, wiring design, clock tree design, etc. - Verification: functional verification and timing verification of the design. - Back-end process: including design data format conversion, physical verification, chip sample manufacturing, etc. 2. The goal of clock tree synthesis is to generate a high-quality clock signal in the chip, and make the propagation delay of the clock signal in the entire chip as small as possible and the waveform quality as good as possible. The goal of clock tree synthesis is to minimize the total delay of the clock path to ensure the normal operation of the chip. 3. The technologies involved in EDA research and development include but are not limited to: - Logic synthesis: convert the RTL design of the high-level description language into a gate-level netlist for logic optimization and synthesis. - Physical design: including layout design, wiring design, clock tree design, etc., to achieve the planning and optimization of the physical structure of the chip. - Verification: functional verification and timing verification of the design to ensure the correctness and stability of the chip. - Simulation and debugging: Verify and debug the design through simulation and debugging tools. 4. The life cycle of a chip can be divided into several stages: design, manufacturing, testing, deployment and use. Among them, the stage with the lowest probability of failure is generally the manufacturing stage, because the chips undergo rigorous testing and screening during the manufacturing process to ensure that their quality meets the specified standards. 5. In convolutional neural networks (CNNs), padding refers to adding additional pixel values around the edges of the input image to better process edge pixels. Common padding methods include: - Valid Padding: Without padding, the output size will be smaller than the input size. - Same Padding: Add padding around the input so that the output size is the same as the input size. 6. Pipelining is a design technique that divides a computing or processing task into multiple stages, each of which is executed in parallel. Theoretically, the number of pipeline stages can be increased indefinitely, but in practice it is limited by many factors, including: - Data dependency: Some tasks may depend on the output results of the previous stage and cannot be executed in parallel. - Resource constraints: Each stage requires a certain amount of resources, such as processing units, registers, etc., and limited resources may limit the number of pipeline stages. - Timing constraints: Each stage has a certain clock cycle, and the overall frequency of the pipeline will be limited by the slowest stage. - Error handling and conflict handling: Error and conflict handling in the pipeline requires additional logic to implement, which may increase latency and complexity. I changed my nickname to eew_V04Cyi