MSP430F5529 clock multiplier setting is effective

火辣西米秀

MSP430F5529 clock multiplier setting is effective [Copy link]

void initClock()
{
UCSCTL6 &= ~XT1OFF; //Start XT1
P5SEL |= BIT2 + BIT3; //XT2 pin function selection
UCSCTL6 &= ~XT2OFF; //Turn on XT2
// PMMCTL0 |=PMMPW+ PMMCOREV_3;
PMMCTL0_H = 0xA5; //Turn on PMM power management
SVSMLCTL |= SVSMLRRL_1 + SVMLE; //Configure SVML voltage
PMMCTL0 = PMMPW + PMMCOREV_2; //Configure core voltage
while((PMMIFG & SVSMLDLYIFG ) == 0); //Wait for setting to complete
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG + SVSMLDLYIFG);
if((PMMIFG & SVMLIFG) == 1) //Judge whether the core voltage rises to VSVML
while((PMMIFG & SVMLVLRIFG) == 0); //If not waiting for
SVSMLCTL &= ~SVMLE; //Turn off SVML modulePMMCTL0_H
= 0X00; //Latch configuration__bis_SR_register
(SCG0);
UCSCTL0 = DCO0+DCO1+DCO2+DCO3+DCO4; //Select DCO frequency regionUCSCTL1
= DCORSEL_5; //DCO frequency range is below 28.2MHZUCSCTL2
= FLLD_4 + 2; //D=16, N=1 16*2*（4/8)=
16UCSCTL3 = SELREF_5 + FLLREFDIV_3; //n=8, FLLREFCLK clock source is XT2CLK; DCOCLK=D*(N+1)*(FLLREFCLK/n); DCOCLKDIV=(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELA_4 + SELS_3 +SELM_3; //The clock source of ACLK is DCOCLKDIV, the clock source of MCLK\SMCLK is DCOCLK
UCSCTL5 = DIVA_5 +DIVS_1; //ACLK is obtained by dividing DCOCLKDIV by 32, and SMCLK is obtained by dividing DCOCLK by 2
//Finally, MCLK: 24MHZ, SMCLK: 12MHZ, ACLK: 48KHZ

__bic_SR_register(SCG0); //Enable the FLL control loop

}

void initClock()
{
UCSCTL6 &= ~XT1OFF; //Start XT1
P5SEL |= BIT2 + BIT3; //XT2 pin function selection
UCSCTL6 &= ~XT2OFF; //Turn on XT2
// PMMCTL0 |=PMMPW+ PMMCOREV_3;
PMMCTL0_H = 0xA5; //Turn on PMM power management
SVSMLCTL |= SVSMLRRL_1 + SVMLE; //Configure SVML voltage
PMMCTL0 = PMMPW + PMMCOREV_2; //Configure core voltage
while((PMMIFG & SVSMLDLYIFG ) == 0); //Wait for setting to complete
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG + SVSMLDLYIFG);
if((PMMIFG & SVMLIFG) == 1) //Judge whether the core voltage rises to VSVML
while((PMMIFG & SVMLVLRIFG) == 0); //If not waiting for
SVSMLCTL &= ~SVMLE; //Turn off SVML modulePMMCTL0_H
= 0X00; //Latch configuration__bis_SR_register
(SCG0);
UCSCTL0 = DCO0+DCO1+DCO2+DCO3+DCO4; //Select DCO frequency areaUCSCTL1
= DCORSEL_4; //DCO frequency range is below 28.2MHZUCSCTL2
= FLLD_4 +1; //D=16, N=1 16*2*（4/8)=
16UCSCTL3 = SELREF_5 + FLLREFDIV_3; //n=8, FLLREFCLK clock source is XT2CLK; DCOCLK=D*(N+1)*(FLLREFCLK/n); DCOCLKDIV=(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELA_4 + SELS_3 +SELM_3; //The clock source of ACLK is DCOCLKDIV, the clock source of MCLK\SMCLK is DCOCLK
UCSCTL5 = DIVA_5 +DIVS_1; //ACLK is obtained by dividing DCOCLKDIV by 32, and SMCLK is obtained by dividing DCOCLK by 2
//Finally, MCLK: 16MHZ, SMCLK: 8MHZ, ACLK: 32KHZ

__bic_SR_register(SCG0); //Enable the FLL control loop

}

void initClock()
{
UCSCTL6 &= ~XT1OFF; //Start XT1
P5SEL |= BIT2 + BIT3; //XT2 pin function selection
UCSCTL6 &= ~XT2OFF; //Turn on XT2
PMMCTL0_H = 0xA5; //Turn on PMM power management
SVSMLCTL |= SVSMLRRL_1 + SVMLE; //Configure SVML voltage
PMMCTL0 = PMMPW + PMMCOREV_2; //Configure core voltage
while((PMMIFG & SVSMLDLYIFG ) == 0); //Wait for setting to complete
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG + SVSMLDLYIFG);
if((PMMIFG & SVMLIFG) == 1) //Judge whether the core voltage rises to VSVML
while((PMMIFG & SVMLVLRIFG) == 0); //If not waiting
SVSMLCTL &= ~SVMLE; //Turn off SVML modulePMMCTL0_H
= 0X00; //Latch configuration__bis_SR_register
(SCG0);
UCSCTL0 = DCO0+DCO1+DCO2+DCO3+DCO4;
UCSCTL1 = DCORSEL_4; //DCO frequency range is below 28.2MHZUCSCTL2
= FLLD_4 + 1; //D=16, N=
1UCSCTL3 = SELREF_5 + FLLREFDIV_3; //n=8, FLLREFCLK clock source is XT2CLK; DCOCLK=D*(N+1)*(FLLREFCLK/n); DCOCLKDIV=(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELA_4 + SELS_3 +SELM_3; //ACLK clock source is DCOCLKDIV, MCLK\SMCLK clock source is DCOCLK
UCSCTL5 = DIVA_5 +DIVS_4; //ACLK is obtained by dividing DCOCLKDIV by 32, SMCLK is obtained by dividing DCOCLK by 2
//Finally MCLK: 16MHZ, SMCLK: 1MHZ, ACLK: 32KHZ

__bic_SR_register(SCG0); //Enable the FLL control loop

}