Requirements for Wafer Level Chip Scale Packaging in SRAM
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When talking about the future of wearable technology, the future course of wearable technology innovation is clearly stated. What is loud and clear is that to be successful, wearable electronics must be small while maintaining performance. This article mainly explains the need for wafer-level chip-scale packaging in SRAM.
In order to reduce the footprint and thus reduce the overall board space, microcontrollers are migrating to smaller process nodes with every other generation. At the same time, they are evolving to perform more complex and powerful operations. As the operations become more complex, there is a pressing need to increase cache. Unfortunately, with each new process node, increasing embedded cache (embedded SRAM) becomes challenging for many reasons, including higher SER, lower yield, and higher power consumption. Customers also have customized SRAM requirements. For MCU manufacturers, offering all possible cache sizes would require them to have a product portfolio that is too large to manage. This drives the need to limit the embedded SRAM on the controller die and cache through external SRAM.
But because external SRAM takes up a lot of board space, using external SRAM faces miniaturization challenges. Due to its six-transistor structure, reducing the size of external SRAM by migrating it to a smaller process node will bring up the same problems that plague miniaturized embedded SRAM.
This brings us to the next alternative to this age-old problem: reducing the chip package to die size ratio in the external SRAM. Typically the size of a packaged SRAM chip is many times (up to 10 times) the size of the die. One popular approach to this problem is to not use packaged SRAM chips at all. It makes sense to take an SRAM chip (1/10 the size) and package it together with the MCU chip using complex multi-chip packaging (MCP) or 3D packaging technology (also known as SiP or system-in-package) . But this approach requires a lot of investment and is only feasible for the largest manufacturers. From a design perspective, it also reduces flexibility because the components in the SiP cannot be easily replaced. For example, if a new technology SRAM becomes available, we cannot easily replace the SRAM chip in the SiP. To replace any die within the package, the entire SiP must be requalified. Requalification requires reinvestment and more time.
So is there a way to save board space while keeping SRAM out of the MCU without getting into trouble with the MCP? What about it? Coming back to the die-to-chip size ratio, we do see room for significant improvement. Why not check if there is a package that can fit snugly on the die? In other words, if you can’t do away with the package, reduce the size ratio.
The current state-of-the-art approach is to reduce the die size of the package by using WLCSP (wafer-level chip-scale packaging). WLCSP refers to the technology of assembling individual units in a package after dicing them from a wafer. The device is essentially a bare die with a bump or ball array pattern, without the use of any bond wires or interposers to connect. Depending on the specifications, the chip-scale package part is up to 20% larger in area than the die. Today’s technology has reached a level of innovation where manufacturing plants can produce CSP devices without increasing the chip area (only a slight increase in thickness to fit the bumps/balls).
Figure. Wafer-level chip-scale packaging (WLCSP) offers the most advanced method of reducing the size of the packaged die. The WLCSP shown here was developed by Deca Technologies and does not increase the area of the chip that makes it up. (Source: Deca Technologies/Cypress Semiconductor)
CSPs offer certain advantages over bare dies. CSP devices are easier to test, handle, assemble, and reprogram. They also have enhanced thermal conductivity characteristics. When the die moves to a newer process node, the size of the CSP can be standardized while the die shrinks. This ensures that the CSP part can be replaced by a newer generation of CSP parts without any complications associated with changing the die.
Clearly, these space savings are very important when it comes to the demands of wearables and portable electronics. For example, the 48-ball BGA used for memory in many of today's wearables has dimensions of 8mmx6mmx1mm (48mm3). In contrast, the same part in a CSP-type package measures 3.7mmx3.8mmx0.5mm (7mm3). In other words, the volume can be reduced by 85%. This savings can be used to reduce the PCB area and thickness of portable devices. As a result, manufacturers
of wearable devices and the Internet of Things (IoT) are seeing new demands for WLCSP-based devices beyond just SRAM .
Related article: Understanding SRAM memory from three levels
Since its establishment, Yuxin Co., Ltd. has focused on acting as an agent for semiconductor components of major domestic and foreign brands. The agent brands include NETSOL, JSC, everspin, Lyontek, ISSI, CYPRESS, VTI and other brands with general agent qualifications. The main product lines are sram, mram, psram and other memory chips. We are committed to providing customers with products with competitive advantages. We are a professional storage solution provider.
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