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Can the EPCS16SI8N chip be read and written directly? Altera configuration chip [Copy link]

I just came into contact with FPGA, and I thought that every time FPGA is powered on, it needs to read the configuration from an external configuration chip, such as the EPCS16SI8N chip. I am curious about a few questions: 1. Does the EPCS16SI8N chip actively send after power-on, because the FPGA is not in the configuration state; or is there a fixed power-on read operation in the FPGA, similar to the assembly startup code or something like that? But does this take milliseconds? 2. Since the configuration is written in EPCS16SI8N, can't I remove this chip and make a driver to directly read the configuration information? Or is there a read protection or must it be read according to a certain timing? It doesn't seem safe. Can a big guy help satisfy my curiosity?

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The FPGA is actively read when powered on. EPCS16SI8N is similar to eeprom. Safety is indeed a problem. At least it can be used after being dismantled and moved to another place.   Details Published on 2022-5-13 09:55
 

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The FPGA is actively read when powered on. EPCS16SI8N is similar to eeprom. Safety is indeed a problem. At least it can be used after being dismantled and moved to another place.

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Oh, then I'll look at the chip data to see if I can drive it and clone it.  Details Published on 2022-5-13 10:39
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chenzhufly posted on 2022-5-13 09:55 FPGA actively reads when powered on. EPCS16SI8N is similar to eeprom. Safety is indeed a problem. At least it can be used after being dismantled and moved to another place

Oh, then I'll look at the chip data to see if I can drive it and clone it.

This post is from FPGA/CPLD
 
 
 

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