Design of filter module based on combination of single chip microcomputer and FPGA

Aguilera

Design of filter module based on combination of single chip microcomputer and FPGA [Copy link]

With single-chip microcomputer and programmable logic device (FPGA) as the control core, a programmable filter is designed to realize the functions of small signal programmable amplification, programmable adjustment of filter cutoff frequency and amplitude-frequency characteristic test. The amplification module is realized by variable gain amplifier AD603, with a maximum gain of 60dB, adjustable in 10dB steps, and a gain error of less than 1%. The programmable filter module is composed of MAX297 low-pass filter, TLC1068 high-pass filter and elliptical low-pass filter, and the filter mode is selected by analog switch. This system programmably adjusts the -3dB cutoff frequency of the active filter so that it can be adjusted in the range of 1~30kHz, with an error of less than 1.5%. In addition, the effective value sampling chip AD637 and the 12-bit parallel A/D converter MAX120 are used to measure the amplitude of the swept frequency signal.
　　The filter is a device used to eliminate interference noise, which can be used to effectively filter out the frequency point of a specific frequency or the frequency outside the frequency point. It occupies an important position in the field of electronics and has been widely used in signal processing, anti-interference processing, power system, and anti-aliasing processing. As for the programmable filter, the biggest feature of the system is that its filtering mode can be selected by programmable control, and the -3 dB cutoff frequency can be adjusted by programmable control, which is equivalent to a filter with multiple functions in one, and will have better application prospects. In addition, the system has the function of testing the amplitude-frequency characteristics, and displays the spectrum characteristics through an oscilloscope, which can intuitively reflect the filtering effect.
　　1 Scheme demonstration and selection
　　1.1 Design and demonstration of variable gain amplifier module
　　Scheme 1: Digital potentiometer controls the two-stage INA129 cascade. Use FPGA to control the digital potentiometer DS1267 to output different resistance values as the feedback resistor of the high-precision instrument amplifier INA129. By controlling the digital potentiometer to change the amplification factor of INA129, the gain of the amplifier can be adjusted.
　　Scheme 2: Use variable gain amplifier AD603 to achieve. The variable gain amplifier is composed of an R-2R ladder resistor network and a fixed gain amplifier. The signal added to the input end of the ladder network is attenuated and output by the fixed gain amplifier. The attenuation is determined by the reference voltage added to the gain control interface. The gain can be controlled by a single-chip microcomputer, and the DAC generates an accurate reference voltage to control the gain, thereby achieving more accurate digital control.
　　Since the input sinusoidal small signal amplitude is 10 mV, the voltage gain is 60 dB, and the 10 dB step process control is adjustable, and the voltage gain error cannot be greater than 5%. In terms of accuracy, both schemes can be realized. Adding one more stage of amplification after AD603 can also achieve an amplification factor of 60 dB. However, the internal structure of the digital potentiometer is complex and affected by capacitance. Connecting the post-stage to the op amp will bring unexpected consequences, so scheme 2 is adopted.
　　1.2 Design and demonstration of filter module
　　Scheme 1: Use digital filter. Use MATLAB's digital filter to design FIR or IIR filter. Digital filters have the advantages of high accuracy and good cutoff characteristics. However, FIR filters will take up too many FPGA resources. IIR filters require a lot of work and are not very stable when designed. In addition, different parameters must be used to make the cutoff frequency adjustable, so the software required for design is relatively large.
　　Option 2: Use passive LC filters. Various types of filters can be built using inductors and capacitors. By referring to the relevant parameters in the filter design manual, it is relatively easy to design an ideal filter. However, if the cutoff frequency is to be adjustable, the hardware will be very complicated only by changing the inductor and capacitor parameters.
　　Option 3: Use an integrated switched capacitor filter chip. The switched capacitor filter is a large-scale integrated circuit filter composed of MOS switches, MOS capacitors and MOS operational amplifiers. Driven by the clock frequency, its switched capacitor group can be equivalent to an equivalent resistor related to the clock frequency. When the external clock is changed, the equivalent resistance changes, thereby changing the time constant of the filter, and thus changing the filtering characteristics. The switched capacitor filter can directly process analog signals without the need for A/D and D/A conversion like digital filters, which simplifies the circuit design and improves the reliability of the system.
　　In summary, this system adopts scheme 3, using the integrated chip MAX297 to realize the low-pass filter and LTC1068 to realize the high-pass filter; scheme 2 is adopted to use passive LC filter technology to realize the fourth-order elliptical low-pass filter.
　　2 System overall design scheme and implementation block diagram
　　This system uses a single-chip microcomputer and FPGA as the control core, and is composed of a controllable gain amplifier module, a program-controlled filter module and an amplitude-frequency characteristic test module. The system block diagram is shown in Figure 1. The input amplitude of 1 V is attenuated by the voltage divider network and becomes a small signal with an amplitude of 10 mV. It is amplified by 2 times by the OPA690 front stage, and plays the role of impedance transformation and isolation. At the same time, AD9851 generates a sinusoidal signal of a set frequency, which is sent to the back stage through an analog switch. The signal is controlled by the program to perform an adjustable gain amplification of 0 to 60dB by AD603 and then sent to the filter module. The filter module includes low-pass, high-pass and elliptical filters, among which the low-pass and high-pass are controlled by the program and the -3 dB cutoff frequency is adjustable in the range of 1 to 30 kHz, with a step of 1kHz. The cutoff frequency of the elliptical filter is 50 kHz. Then a specific filter signal output is selected through the analog switch, and after RMS detection and A/D conversion, it is sent to the FPGA for amplitude-frequency characteristic testing, and then two DAC0800s are used to display the amplitude-frequency characteristic curve.
　

　　3 Main Function Circuit Design
　　3.1 Amplification Module
　　The specific circuit of the amplification module is shown in Figure 2. The first part is a voltage divider network, in which the first four resistors attenuate the input signal by 100 times and form a 51Ω impedance together with the internal resistance of the signal source, and the latter 51Ω is a matching resistor. The second part uses OPA690 to amplify the small signal by 2 times, and at the same time plays the role of impedance transformation and isolation. Since the input impedance of AD603 is 100Ω, a 100Ω resistor is connected in series at the back for matching. The third part is the AD603 variable gain amplifier, and its gain increases linearly in dB as the control voltage increases. The reference voltage of pin 1 is obtained by calculating and controlling the output voltage of the DAC chip through the single-chip microcomputer, thereby realizing precise digital control. Gain G (dB) = 40VG + G0, where VG is the differential input voltage, ranging from -500 to 500mV; G0 is the gain starting point, which is different when connected to different feedback networks. A 5kΩ potentiometer is connected between pins 5 and 7 to change.
　

　　3.2 High-pass filter module
　　LTC1068 is a low-noise, high-precision universal filter. When it is used for high-pass filtering, the cutoff frequency range is 1 Hz to 50 kHz, and there is no aliasing phenomenon up to 200 times the cutoff frequency. Since the four channels of LTC1068 are low-noise, high-precision, high-performance second-order filters, each channel can achieve the functions of low-pass, high-pass, band-pass and band-stop filters by connecting a number of resistors. The specific circuit is shown in Figure 3. The Q value of port B is 0.57, and the Q value of port A is about 1. In the debugging of the circuit, it was found that the Q value of port A needs to be larger than the Q value of port B, otherwise the amplitude of the signal will rise at the cutoff frequency.
　

　　The ratio of the clock frequency to the passband of LTC1068 is 200:1. Since the LTC1068 doubles the clock signal CLK internally, when the minimum cutoff frequency is 1 kHz, the internal clock frequency is actually 400kHz. Therefore, a low-pass filter with a cutoff frequency of 450kHz is added after the LTC1068 to filter out the noise and high-order harmonics caused by the frequency division.
　　3.3 Low-pass filter module
　　Use MAX297 to implement a low-pass filter. The switched capacitor filter MAX297 can be set as an 8th-order low-pass elliptical filter with a stopband attenuation of -80dB and a clock frequency to passband frequency ratio of 50:1. By changing the frequency of CLK, the filter -3 dB cutoff frequency can be adjusted in the range of 1 to 20kHz, with a step of 1 kHz.
　　When using MAX297, it should be noted that when the signal frequency and the sampling resolution are the same frequency, the switched capacitor group samples the same signal amplitude on the capacitor each time, which is equivalent to the case where the input signal is DC, so that the filter outputs a DC level. Similarly, when the signal frequency is an integer multiple of the sampling frequency, the same phenomenon will occur. For this reason, an analog low-pass filter should be added in front of it to effectively exclude high-frequency signals at and above the sampling frequency. Therefore, another MAX297 is used, and the cutoff frequency is set to 50kHz. The clock frequency is set to 2.5 MHz. A low-pass filter should also be added behind it, with a cutoff frequency of 150 kHz to filter out the high-frequency components of the signal and make the waveform smoother. The specific circuit is shown in Figure 4.
　

　　3.4 Fourth-order elliptical low-pass module
　　The system requires the production of a fourth-order elliptical low-pass filter with an in-band fluctuation of ≤1 dB and a -3 dB passband of 50 kHz, which is implemented using a passive LC elliptical low-pass filter. Use Filter Solution to simulate the filter, then simulate it again in MulTIsim and adjust the parameters of the capacitor and inductor to their nominal values. In addition, the emitter follower is connected before and after the elliptical filter to avoid the influence of the previous and next stages. The specific circuit is shown in Figure 5.
　

　　4 System software design
　　The system software design consists of a single-chip microcomputer and an FPGA. Users can select high-pass, low-pass and elliptical filters through the interface display, set the cutoff frequency, and display the amplitude-frequency curve. The single-chip microcomputer mainly completes the user's input and output processing and system control, and the main functions of the FPGA are: controlling the AD9851 to generate a sweep signal, controlling the generation of the filter cutoff frequency clock signal, and controlling two D/A blocks to display the amplitude-frequency characteristic curve. The program flow chart is shown in Figure 6.
　　

　　5 Test plan and test results
　　5.1 Amplifier test
　　The frequency of the sine signal at the input of the amplifier is 10 kHz, the amplitude is 10 mV, and the gain is set to 10, 20, 30, 40, 50, and 60 dB. The actual output amplitude is measured with an oscilloscope, and the actual gain is calculated. The error is less than 1%. In addition, the passband of the amplifier is measured to be 1 to 200 kHz.
　　5.2 Low-pass and high-pass filter test The
　　amplifier gain is set to 40 dB, the filter is set to a low-pass filter, and the filter cutoff frequency is preset in the range of 1 to 30 kHz, with a step of 1 kHz. The actual cutoff frequency is measured with an oscilloscope, and the relative error is calculated to be less than 1.5%, and the total voltage gain at 2fc is less than 20 dB. The high-pass filter test method is similar.
　　5.3 Elliptical filter test
　　The amplifier gain is set to 40 dB, and the actual -3 dB cutoff frequency and the total voltage gain at 200 kHz are measured with an oscilloscope. The measured fc=50.0kHz, the amplitude has almost decayed to 0 at 150 kHz.
　　5.4 Amplitude-frequency characteristic and phase-frequency characteristic test
　　The frequency characteristics of low-pass and high-pass filters are measured, and their amplitude-frequency characteristic curves are displayed on the oscilloscope, which are consistent with the set filter mode and cutoff frequency.
　　6 Conclusion
　　The amplifier gain range of this system is 10-60 dB, the passband is 1-200 kHz, and the gain error is less than 1%. The filter cutoff frequency range is 1-30kHz, and the error is less than 1.5%. The cutoff frequency error of the elliptical filter is 0, and the amplitude is almost decayed to 0 at 150 kHz. The error is mainly due to the clock frequency. When the cutoff frequency is 20 kHz, the highest clock frequency required is 2MHz, which cannot guarantee a good clock edge, and the clock frequency cannot be accurately controlled, as well as the nonlinear error of the amplifier. In addition, the amplitude-frequency characteristic tester is realized using DAC0800 and the effective value detection circuit, and the overall performance of the system is good. Under the organic combination and coordinated control of the single-chip microcomputer and FPGA, the entire system operates stably, has high measurement accuracy, and flexible human-computer interaction.