LDO Basics: Noise - Part 1

alan000345

LDO Basics: Noise - Part 1 [Copy link]

 By Aaron Paxton, Texas Instruments In an LDO Basics blog post, I discussed using a low dropout regulator (LDO) to filter the ripple voltage caused by a switch-mode power supply. However, this is not the only thing to consider when getting clean DC power. Because LDOs are electronic devices, they also generate a certain amount of noise themselves. Choosing to use a low-noise LDO and taking steps to reduce internal noise can both form an integral part of cleaning the power rails without compromising system performance. Identifying Noise An ideal LDO would have voltage rails with no AC components. The downside is that LDOs generate intrinsic noise, just like any other electronic device. Figure 1 shows how this noise looks in the time domain. Figure 1: Output noise snapshot of a noisy power supply Analysis in the time domain is difficult. Therefore, there are two main ways to examine the noise: across the entire spectrum, and as a composite value. You can use a spectrum analysis tool to identify the various AC components in the LDO output line. (The application report, “How to Measure LDO Noise,” provides a wealth of information on noise measurements.) Figure 2 plots the output noise of the 1A low-noise LDO TPS7A91.

Figure 2: TPS7A91Noise spectral density vs. frequency and VOUT

[ align=left]As you can see from the various curves, the output noise (expressed in μV/Hz) is concentrated at the low end of the frequency spectrum. Most of this noise comes from the internal reference voltage, as well as the error amplifier FET and the resistor divider.

Analyzing the output noise across the entire frequency spectrum can help us determine the noise curve for the noise range of interest. For example, designers of audio applications are concerned with the audible frequencies (20Hz to 20kHz), and power supply noise can degrade the sound quality. When comparing Apple devices to Apple devices, data sheets typically provide a single, combined noise value. Output noise is typically combined from 10 Hz to 100 kHz and expressed in microvolts rms (μVRMS). (Various vendors will also combine noise from 100 Hz to 100 kHz or combine noise from a custom frequency range. Combining over the selected frequency range can help mask unpleasant noise attributes, so it is important to examine noise curves in addition to the combined value.) Figure 2 shows the combined noise values for each curve. Texas Instruments offers a family of LDOs with combined noise values as low as 3.8 μVRMS. 85)]Noise Reduction

In addition to selecting an LDO with low noise quality, there are several techniques you can employ to ensure that your LDO has the lowest noise characteristics. These techniques include the use of noise reduction and feed-forward capacitors. I will explore the use of feed-forward capacitors in my next blog post.

Noise Reduction Capacitors

Many of TI’s low noise LDO families have dedicated pins specifically used as “NR/SS” as shown in Figure 3 shown.

[color=rgb(85, 85,Figure 3: NMOS LDO with NR/SS pin This pin has two functions: it is used to filter noise from the internal reference voltage and to reduce the slew rate during startup or enabling the LDO. Adding a capacitor (CNR/SS) to this pin forms an RC filter with internal resistance that helps shunt unwanted noise generated by the reference voltage. Since the reference voltage is the dominant source of noise, adding capacitance pushes the cutoff frequency of the low-pass filter on the left. Figure 4 shows the resulting effect of this capacitor on the output noise. Figure 4: TPS7A91 Noise Spectral Density vs. Frequency and CNR/SS As shown in Figure 4, higher CNR/SS values produce more ideal noise values. After a certain point, increasing the capacitance no longer reduces the noise. The remaining noise comes from the error amplifier, FETs, etc.

Adding capacitors also creates a resistance-capacitance delay during startup, which causes the output voltage to rise at a slower rate. When large capacitance is present in the output or load, it is beneficial to reduce the startup current.

In Equation 1, the startup current is equal to:

To reduce the startup current, you must either reduce the output capacitance or reduce the slew rate. Fortunately, CNR/SS helps achieve the latter, as shown in Figure 5 TPS7A85.

Figure 5: TPS7A85 startup vs. CNR/SS

[align= left]As you can see, increasing the CNR/SS value will increase the startup time, preventing the peak startup current and potentially triggering the current limit.As shown in Figure 4, higher CNR/SS values produce more desirable noise values. At a certain point, increasing the capacitance no longer reduces the noise. The remaining noise comes from the error amplifier, FETs, etc.

Adding capacitors also creates a resistance-capacitance delay during startup, which causes the output voltage to rise at a slower rate. When large capacitance is present in the output or load, it is beneficial to reduce the startup current.

The starting current in equation 1 is equal to:

[color=rgb(85, 85, To reduce startup current, you must either reduce output capacitance or reduce slew rate. Fortunately, CNR/SS helps achieve the latter, as shown in Figure 5 TPS7A85.

[color=rgb(85, 85, Figure 5: Startup vs. CNR/SS for the TPS7A85 As you can see, increasing the CNR/SS value increases the startup time, preventing the startup current spike and potentially triggering the current limit.As shown in Figure 4, higher CNR/SS values produce more desirable noise values. At a certain point, increasing the capacitance no longer reduces the noise. The remaining noise comes from the error amplifier, FETs, etc.

Adding capacitors also creates a resistance-capacitance delay during startup, which causes the output voltage to rise at a slower rate. When large capacitance is present in the output or load, it is beneficial to reduce the startup current.

The starting current in equation 1 is equal to:

[color=rgb(85, 85, To reduce startup current, you must either reduce output capacitance or reduce slew rate. Fortunately, CNR/SS helps achieve the latter, as shown in Figure 5 TPS7A85.

[color=rgb(85, 85, Figure 5: Startup vs. CNR/SS for the TPS7A85 As you can see, increasing the CNR/SS value increases the startup time, preventing the startup current spike and potentially triggering the current limit.

月下良缘

Thanks for sharing