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MSP430F149 clock program architecture [Copy link]

Program architecture Generally, the system clock needs to be configured after the watchdog is turned off after system initialization. The configuration steps are: 1. Turn on the crystal oscillator; 2. Wait for the crystal oscillator to start. Clear OFIFG, delay, and determine whether OFIFG is 0. If it is 0, the crystal oscillator starts normally and exits the judgment; 3. Select MCLK/SMCLK clock source; uchar iq0; BCSCTL1&=~XT2OFF; do IFG1 &= ~OFIFG; for (iq0 = 0xFF; iq0 > 0; iq0--); // Delay, wait for XT2 to start oscillating } while ((IFG1 & OFIFG) != 0); // Determine whether XT2 starts oscillating BCSCTL2 =SELM_2+SELS; // Select MCLK and SMCLK for XT2 2.2 Detailed description For DCO, different frequencies can be obtained by configuring resistors and DCO. The resistors can be configured on-chip or off-chip (DCOR is generally on-chip), there are 8 on-chip resistors to choose from (RSELX), and there are 8 DCOs to choose from (DCOX). 3. Related registers 1. DCOCTL DCOx Bits 7-5 DCO frequency select. These bits select which of the eight discrete DCO frequencies of the RSELx setting is selected. 2. BCSCTL0 XT2OFF Bit 7 XT2 off. This bit turns off the XT2 oscillator 0 XT2 is on 1 ] The value of the resistor defines the nominal frequency. Select MCLK. 2 oscillator not present on-chip. 11 LFXT1CLK SELS Bit 3 Select SMCLK. This bit selects the SMCLK source. 0 DCOCLK 1 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK when or 1 External resistor 4. Example 4.1 Configure MCLK/SMCLK See Section 2.1。


4.2配置DCO


void main(void)


{


  WDTCTL = WDTPW +WDTHOLD;                  // Stop Watchdog Timer


  DCOCTL = DCO0 + DCO1 + DCO2;              // Max DCO


  BCSCTL1 = RSEL0 + RSEL1 + RSEL2;          // XT2on, max RSEL


  BCSCTL2 |= SELS;                          // SMCLK = XT2


  P5DIR |= 0x70;                            // P5.6,5,4 outputs


  P5SEL |= 0x70;                            // P5.6,5,5 options


  while(1)


  {


  }


}


实测DCO最低128K,最高4.58M。

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