I connected my AXI master module to the fpga2hps bridge of hps on the Qsys system. The system can pass the compilation. But when generating the dts file, it always reports that the module I wrote is u
The designed board has reached the SRIO debugging stage. On the board, one V6 and two 6678s are interconnected through 4XSRIO. There is no Switch in between, and finally the communication between them
In the Internet age, our microcontrollers also need to access the Internet. The attachment compares several practical solutions for implementing TCP-IP in embedded systems. This information is rare!
After waiting for so long, I finally arrived at EEWORLDSorry for the long wait.Just post a message and it will be delivered immediately. Please make good use of it. It is not easy.Looking forward to m