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  • Logic Synthesis Part 2
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  • Duration:24 minutes and 14 seconds
  • Date:2024/05/04
  • Uploader:抛砖引玉
Introduction
keywords: VLSI
Bar-Ilan University 83-612: Digital VLSI Design

In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).

Lecture slides can be found on the EnICS Labs web site at: 
https://enicslabs.com/academic-courses/dvd-english/

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