[color=#000][font=Tahoma][size=3]Pipeline operation can be said to be the privilege of Verilog HDL language. It is difficult to implement pipeline operation in sequential operation such as C language.
[i=s]This post was last edited by ljj3166 on 2015-1-7 22:17[/i] [b][size=4]There don't seem to be many posts about disassembly in the forum. I'm going to post one today. Actually, I've been a wrecker
hi:I drew a 315M module by myself based on TI's CC1101 demo board. The inductor and capacitor are both 0402, and the inductor is Murata's winding inductor. Now I tested the communication distance and
[b]Table of Contents[/b] Chapter 1 Programmable Logic Design Guidelines 1 1.1 Basic Programmable Logic Design Principles 1 1.1.1 The principle of balancing and interchanging area and speed 1 1.1.2 Har
I'm really depressed. I've made a few boards recently. I encountered this problem. I used F28015, and I didn't have this problem in previous product designs.Now I've made a few new boards, but I have
I made a lot of things when I was learning 51, but many of them did not leave complete data. Here I post a thing I made with complete data, and I will post the things I have sorted out later. Although