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How to express it with Verilog code: A continuously sent data packet is generated in the FPGA, the size is 7190, the packet header is 32 bits, the data in the packet body is a continuously increasing
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[i=s]This post was last edited by df_flying on 2017-9-26 22:46[/i] [size=4] From the schematic diagram, we can see that the MAX32630FTHR has a BMI160 on board, which is connected to IIC2 together with