Location:Training / Using MATLAB for FPGA design / Generate and synthesize RTL

This video series will show you how to deploy signal processing algorithms to your FPGA design. Using the pulse detection algorithm as an example, this tutorial series begins with the basics required for successful FPGA design and then moves on to adapting the algorithm so that it can be deployed automatically.

HDL Coder™ generates synthesizable VHDL® or Verilog® RTL from MATLAB® functions, Simulink® models, and Stateflow® diagrams, targeting FPGA or ASIC hardware.

HDL Coder™ generates synthesizable VHDL® or Verilog® RTL from MATLAB® functions, Simulink® models, and Stateflow® diagrams, targeting FPGA or ASIC hardware. 
This tutorial uses a simple signal processing algorithm to demonstrate the typical steps that customers follow to adapt their high-level algorithms to hardware architectural details so that they can be efficiently implemented in hardware and verified at each step.
This video covers:
- Key considerations for hardware design: streaming data and fixed resources -
Advantages of MATLAB and Simulink and how to leverage them for hardware design
- Overview of the workflow, including verification of each step -
Overview of HDL Coder self-study tutorials -
MATLAB Introduction to the Golden Reference Algorithm
- Adapting Frame-Based Algorithms to Streaming Algorithms

To effectively apply the algorithm to FPGA or ASIC hardware, it needs to be adapted to handle streaming data and optimized for the amount of fixed resources required. Simulink® helps visualize hardware architecture and data flow. If your original algorithm was developed in MATLAB®, you can reuse much of your work when you modify the algorithm for hardware implementation using Simulink.

This video covers:
- Sharing workspace variables between MATLAB and Simulink
- Leveraging hardware design experience to tune algorithms for efficient implementation
- Logging signals as test points for debugging
- Visualizing data types and how they propagate through the design
- In-flow Reuse MATLAB code in MATLAB function blocks
- Use MATLAB testbench to simulate and verify the output of Simulink hardware implementations

Generating effective FPGA designs often requires balancing data throughput, latency, and hardware resources. Depending on the nature and goals of the design, there are various ways to adapt the algorithm to an efficient hardware implementation. This part of the tutorial shows some methods.

This video covers:
-Setting model parameters for HDL code generation
-How the sample rate of the Simulink® model translates to the clock rate of the FPGA hardware
-Inserting pipeline registers on the data path using various optimization techniques
-Using data valid control signals to monitor Enter sample data
—validate the optimized architecture using the MATLAB® testbench
Efficient hardware implementation requires quantizing your data type to fixed point. Signal processing algorithms can be challenging to convert while maintaining the required accuracy, especially if you are writing RTL by hand. Model-based design methods allow you to easily explore and visualize different options and automate much of the process. This part of the tutorial shows the basic concepts and the general methods that can be used.

This video covers:
-Converting the default 64-bit double data type to a fixed-point
representation -Fixed-point data type definitions in the MATLAB® and Simulink® environments
-Propagating data types to maintain precision during mathematical calculations
-Consistency and accuracy Perform model checking to ensure predictable implementation results
—use golden references to compare and validate fixed-point model designs

Traditionally, FPGA programming begins with providing register transfer level (RTL) VHDL® or Verilog® code to the FPGA synthesis tool. In this part of the tutorial, we show how to automatically generate RTL from a proven high-level architectural model, analyze the estimated time and resource usage, and then run synthesis automatically.

This video covers:
- Running code checks for HDL code generation preparation and potential hardware inefficiencies
- Automatically or manually resolving reported issues
- Setting up third-party tools to synthesize generated VHDL or Verilog
- Using the HDL Workflow Advisor to generate the stages of RTL code , Tasks and Setup
- Resource usage and optimization reports that provide fast high-level feedback before synthesis
- Analyze timing and critical paths for FPGA synthesis