I am working on a project that uses the DDR2 IP CORE. In SOPC, I can successfully generate the SOPC system, but the following error occurs when compiling the entire Q2 project. I hope everyone can hel
Hello everyone, since I published "I don't believe I can't make a differential probe", I have received a lot of comments and attention from friends. Thank you all in advance. How is the current situat
[i=s]This post was last edited by tao282515641 on 2014-1-10 14:26[/i] I would like to share all the experimental routines of the FPGA development board. You can refer to them if you need them.
Hello, I have a set of products, the frequency is 433M, the power is 28dB, the network matching is 50Ω, and the radiation effect is not very good. I don't know which expert can solve it. You can consi