Training

Location:Training / Hot Applications / Industrial Control / Introduction to Intelligent Control / Mamdani reasoning

You can log in to your eeworld account to continue watching：
Mamdani reasoning
Login

Duration：11 minutes and 45 seconds
Date：2019/04/27

Uploader：老白菜

Introduction

keywords： control Neural Networks fuzzy control genetic algorithm

There are many kinds of intelligent phenomena in nature, such as the cognitive process of the human brain, bird migration, and lions foraging. So can machines be programmed to imitate the thought processes of these animals? The answer is yes, and this technology that uses programs to simulate natural phenomena in nature to serve the control process is intelligent control technology.

It mainly talks about expert control, fuzzy control, artificial neural network control, genetic algorithm, and teaches MATLAB programming and SIMULINK knowledge to realize the above knowledge.

You Might Like

Recommended Posts

ACIM control problem - about IdRef setting and rotor angle estimation: [align=left][color=rgb(85, 85, 85)][font="][size=14px][b]Hello seniors and experts: [/b][/size][/font][/color][/align] [align=left][color=rgb(85, 85, 85)][font="][size=14px]I have two ACIM control pro; jeyran TI Technology Forum

Can someone show me what power module (SPM) this is?: [i=s]This post was last edited by cciew on 2019-6-5 15:38[/i]Hello everyone, can anyone tell me what power module (SPM) this is? It is currently in use and cannot be removed for inspection! Drive: Thr; cciew Motor Drive Control（Motor Control）

Debugging Problems: [img]C:\Users\mocai\Pictures\IAR_ERR.png[/img] [img]C:\Users\mocai\Pictures\Texas_ok.png[/img]; mocai RF/Wirelessly

Looking for a simulation software: I'm looking for a simulation software. I used Multisim before, but I can't find many components in it. Can someone provide me a simulation software? Thank you!; 曹伟1993 Analog electronics

[Community Lecture] How to add timing constraints in FPGA design environment: When doing logic synthesis and layout and routing for FPGA, you need to set timing constraints in the tool. Usually, in FPGA design tools, FPGA contains four paths: from input port to register, from r; HDLWorld FPGA/CPLD

Problems with debugging programs in RAM mode, pausing programs in software, how to control epwm output: When debugging the program, I clicked Pause in the CCS interface to stop the program. At this time, the epwm output became a constant high level. How can I control it so that after the program is paus; Ark-胡 DSP and ARM Processors

Recommended Content

Hot VideosMore

Hot ArticlesMore

Circuit

可能感兴趣器件

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews

Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函

京公网安备 11010802033920号