• You can log in to your eeworld account to continue watching:
  • Clocked flip-flop—RS flip-flop
  • Login
  • Duration:14 minutes and 23 seconds
  • Date:2018/07/01
  • Uploader:老白菜
Introduction
The course content mainly includes: basic knowledge of digital circuits (number system, coding, logic algebra, logic gates, flip-flops, etc.), combinational circuit analysis and design methods, sequential circuit analysis and design methods, pulse waveform generation and shaping, programmable logic devices and analog-to-digital conversion, etc.

Unfold ↓

You Might Like

Recommended Posts

Want to buy Infineon products? Go to Infineon Tmall flagship store! New store opening, limited time discount!
[font=微软雅黑]If your company is planning to purchase Infineon products; if you want to test Infineon products; if you are planning to use Infineon products in your DIY; if... [/font] [font=微软雅黑]Don't th
EEWORLD社区 Sensor
Microcontrollers (Part 3): LEDs are flashing everywhere
[i=s]This post was last edited by Hai on 2016-3-8 15:02[/i] [font=微软雅黑][size=4][color=#000] There is a poem in the Dunhuang quzi ci "Huanxisha", which goes "The scenery is full of twinkling lights, an
凔海 51mcu
It's Chinese Valentine's Day. Who are you spending it with today? How are you spending it?
Companionship is a wonderful thing. Today is the legendary Chinese Valentine's Day. I wish all the loving engineers in the world will finally get married.As the saying goes: A wish made on Chinese Val
eric_wang Talking
BB-Black has arrived!
BB-Black has arrived! The next step is the arm linux porting and cross-compilation. I have done it on the OK6410 board before. It was also a painful experience. Let's do it again!
wbhb2011 DSP and ARM Processors
The driver of the 430 emulator cannot be installed on win7 32-bit. Please give me some advice.
The driver of the 430 emulator cannot be installed on win7 32-bit. The installation fails every time and the following situation occurs
近猪者痴xp Microcontroller MCU
FPGA power startup timing
Generally, a system has both CPU and FPGA. For a relatively large system, the CPU startup sequence is usually IO voltage first, then the kernel, usually 3.3---2.5---1.8---1.2---1.0V; while the FPGA st
flower_huanghua FPGA/CPLD

Recommended Content

Circuit

可能感兴趣器件

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号