Improve system performance with Altera's new memory controller IP

The othermemory controllerUniPHY

Timing and signaling are critical factors in external memory design. Altera's new memory controller and UniPHY further improve systems by enabling higher clock data rates, reduced latency, ease of use, ease of debugging, voltage and temperature (VT) tracking, and PLL/DLL sharing. performance. In the demonstration, you will learn about the design flow, how to initialize the memory controller, and design and debug it.

Total of 3 lessons44 minutes and 25 seconds