Advanced hybrid physical chip layout design

進階混訊實體晶片佈局設計

• Chapter 1：Introduction (1 hours and 17 minutes and 46 seconds)

• Chapter 2：Manufacturing Process(1) (1 hours and 33 minutes and 30 seconds)

• Chapter 3：Manufacturing Process(2) (1 hours and 28 minutes and 27 seconds)

• Chapter 4：Manufacturing Process(3) (1 hours and 39 minutes and 48 seconds)

• Chapter 5：Mismatch vs Strategies(1) (1 hours and 47 minutes and 38 seconds)

• Chapter 6：Mismatch vs Strategies(2) (1 hours and 3 minutes and 46 seconds)

• Chapter 7：Mismatch vs Strategies(3) (20 minutes and 31 seconds)

• Chapter 8：Failure Mechanisms (41 minutes and 13 seconds)

• Chapter 9：Layout of MOS Transistor(1) (1 hours and 11 minutes and 37 seconds)

• Chapter 10：Layout of MOS Transistor(2) (1 hours and 36 minutes and 41 seconds)

• Chapter 11：Layout of MOS Transistor(3) (1 hours and 22 minutes and 34 seconds)

• Chapter 12：Wire(1) (1 hours and 1 minutes and 45 seconds)

• Chapter 13：Wire(2) (1 hours and 50 minutes and 25 seconds)

• Chapter 14：Wire(3) (46 minutes and 53 seconds)

• Chapter 15：Layout of Resistor (1 hours and 44 minutes and 12 seconds)

• Chapter 16：Layout of Capacito(1) (1 hours and 3 minutes and 48 seconds)

• Chapter 17：Layout of Capacito(2) (1 hours and 26 minutes and 13 seconds)

• Chapter 18：Layout of Capacito(3) (37 minutes and 29 seconds)