Application and Implementation of DSP and FPGA in Image Transmission System

Video communication is a hot topic in the current computer and communication fields. Compared with wired communication, wireless spread spectrum has its inherent advantages, such as convenient networking and low cost. Therefore, the development of wireless spread spectrum real-time image transmission system has high practical value.

System Design

In short-distance communication, parity check, accumulation and check, and other anti-noise measures such as error retransmission can usually be added to the transceiver. However, the above measures can only detect errors, not correct them, which means that the transmission process is not fault-tolerant. In the case of long distance, large interference, and very high error probability, simple error retransmission measures will lose work efficiency and significance. Therefore, a fault-tolerant data transmission method is needed, and the data must be encoded. The use of spread spectrum technology and the selection of high-speed pseudo-random codes with excellent autocorrelation and cross-correlation characteristics to expand the bandwidth of the transmitted signal can enhance the system's anti-interference ability. After compressing the image data, QPSK spread spectrum modulation technology is used.

The DSP of the system consists of two DSPs, the main control DSP and the baseband DSP. The main control DSP belongs to the control center of the system and is used to complete the instructions of the control system interface bus, such as self-test, channel preset, D/A and A/D conversion, working mode switching and AGC. The main control DSP also cooperates with the FPGA to manage the system clock, complete the task coordination and data transmission between the baseband DSP, manage the system bus and distinguish the data, information categories and control interface. The baseband DSP mainly completes the compression encoding of image data and the source and channel encoding and decoding of data, framing and deframing. When sending image data, the DSP controls the data input to undergo random scrambling, bit expansion, encoder tail bit addition, 1/2 convolution encoding and interleaving, and then performs signal stream framing and deframing, and adds control information for continuous synchronous transmission. When receiving data, the DSP operates in the opposite way. After despreading, demodulation and extraction of control information, a continuous image signal stream is formed. The DSP completes deinterleaving, Viterbi decoding, tail bit removal, multi-bit judgment and de-scrambling processing, and restores it to an image signal, which is then decoded by the source and compressed and decoded by the image data.

The FPGA of the system mainly completes RS encoding and clock division. In the baseband signal processing module at the transmitting end, the DSP hands over a frame of information data to the FPGA for RS encoding. The encoding result is m+n bytes (m and n are constants determined by the specific system, the same below), of which the first m bytes are information data and the last n bytes are check code elements. After the FPGA encoding is completed, the DSP is notified to receive the data. After receiving the notification, the DSP receives the encoding result. In the baseband signal processing module at the receiving end, the DSP hands over the data of an RS frame (m+n bytes) to the FPGA for RS decoding. After the FPGA decoding is completed, a decoding result of m bytes is generated, and then the DSP is notified to receive the decoded data. After receiving the notification, the DSP receives the decoding result.

Communication between FPGA and DSP

After the FPGA processes the data, it sends the data to the two DSPs. A FIFO is made in the FPGA. When the FIFO reaches a certain capacity, a reading interrupt is sent to the DSP. The DSP can read the data through the I/O port, and the FIFO capacity is reduced. Then, the FPGA continues to send data to be processed to the FIFO. When the data reaches a certain capacity, an interrupt is sent again, and the cycle continues.

The advantage of using FIFO is that it is easier to process. However, there may be a situation where the sum of the DSP reading speed and processing speed is greater than the FPGA filling speed to the FIFO, or the DSP misses the reading interrupt. Both of these situations will cause the FIFO to be filled and no interrupts will be sent, and the DSP will enter a dead wait state and no longer work. In order to prevent the occurrence of a dead wait state, the following two measures need to be reflected in DSP programming:

1. Try to speed up the reading speed of the DSP I/O port and the processing speed of an interrupt, so that the time is less than the speed of the FPGA inputting the response data to the FIFO. In the design of this system, the FIFO sends 4092 numbers to the DSP at a time, and it takes 330ms for the FPGA to input 4092 numbers to the FIFO. In other words, the time for the DSP to read these 4092 numbers plus the time to process them cannot exceed 330ms. In the subsequent design, many instructions and interface designs of the DSP were optimized, so that the response time of an interrupt was 100ms, which greatly improved the performance of the system.

2. If there are other reasons, such as electrical interference on the board causing the DSP to miss interrupts, it is also possible that the FIFO is full, causing the system to enter a dead wait. In this case, a judgment algorithm should be added to the DSP program. Under normal circumstances, the DSP should respond to an interrupt every 330ms, but if no interrupt arrives for a long time, the DSP must issue a response instruction to restart the FPGA and clear the FIFO.

System synchronization problems and solutions

Since this system uses direct sequence spread spectrum communication technology, the synchronization of the spread spectrum system is a prerequisite for successful communication. If there is no synchronization, the signal code cannot be demodulated, and the anti-interference advantage of the spread spectrum system cannot be brought into play. Due to the inconsistency of the receiving and transmitting clocks, the starting time difference of the spread spectrum sequence, the delay of radio wave propagation and other factors, the spread spectrum sequence started by the receiving end and the received transmission spread spectrum sequence are always out of sync at the beginning. Therefore, the receiving end must adopt certain technical measures to force the local spread spectrum sequence to synchronize with the spread spectrum sequence of the transmitting end, which is the capture of the spread spectrum code. After synchronization is achieved, the interference of noise and some external factors will also force the synchronization that has been achieved to lose lock. For this reason, a technology to maintain synchronization should also be adopted, which is synchronous tracking.

The synchronization process is handled based on the following criteria: if the positions of the five consecutive maximum correlation values ​​are equal, synchronization capture is considered to be achieved; if two of the ten consecutive maximum correlation value positions are not equal, the out-of-sync recapture criterion will be used. There are three main aspects of code synchronization: main synchronization process, phase difference detection and post-fine-tuning processing, and Doppler frequency shift processing.

Conclusion

During the initial debugging of the system, the following problems were encountered:

1. Due to the imbalance of I and Q paths at the modulation end, the output amplitude of the correlation peaks of I and Q paths differs by an order of magnitude, which brings problems to the subsequent data judgment baseband clock extraction.

2. After several sampling analyses, the sampling results are unstable.

3. The data after A/D sampling has a DC component.

According to the synchronization processing idea described in this article, the receiving end obtains a better correlation peak after synchronization processing.

Based on DSP and FPGA, this paper uses intermediate frequency digitization method and QPSK spread spectrum modulation technology to realize wireless transmission of images. These design ideas and results are universal and general.