Design of DSP Multi-SPI Port Communication Based on CPLD

At present, various communication methods are widely used in electrical automation control devices to complete the information transmission between the upper and lower controllers, the lower controllers and the control chip, and realize the corresponding control functions; the design and implementation of various communication functions have become an important part of the design of automation devices. This paper takes an ultrasonic motor motion control device as the application background and discusses the multi-SPI port communication technology of DSP control chip based on CPLD.

Serial Synchronous Peripheral Port (SPI) is also commonly called synchronous peripheral port. It has the characteristics of few signal lines, simple protocol and fast transmission speed. It is widely used in the communication between microcontrollers and peripheral chips. At present, the SPI communication method has been widely accepted, and more and more chips with SPI ports are available, such as Flash, RAM, A/D conversion, LED display, and control-specific DSP chips.

This paper introduces an ultrasonic motor motion control device designed with a motion control dedicated DSP chip DSP56F801. Since the ultrasonic motor needs to use two-phase four-way symmetrical PWM signals to achieve drive control, and the DSP chip cannot directly generate the required PWM signals, and the software method will take up a lot of DSP computing time, a symmetrical PWM signal generator based on a programmable logic device (CPLD) is designed. Under the control of the DSP, the signal generator can realize the duty cycle and phase difference adjustment of the output two-phase PWM control signal; at the same time, the programmable oscillator LTC6903 with an SPI interface is used to realize the PWM control signal frequency adjustment under the control of the DSP. It can be seen that in order to realize the DSP's control of the PWM control signal duty cycle, phase difference and frequency, it is necessary to use an appropriate communication method to realize the control information transmission between the DSP and the CPLD and LTC6903. The DSP56F801 chip has an SPI communication port. Based on the analysis of the SPI data transmission timing relationship, this paper designs and implements multi-SPI interface communication based on CPLD.

1 Working Principle

SPI is a synchronous protocol interface, and all transmissions refer to a common clock. On the same SPI port, a host chip can be connected to multiple slave chips. At this time, the host selects the slave device by triggering the chip select input pin of the slave device. The unselected slave device will not participate in the SPI transmission. The SPI master uses four signals: master output/slave input (MOSI), master input/slave output (MISO), serial clock signal SCLK and peripheral chip select signal (SS). Both the host and the peripheral contain a serial shift register. The host initiates a transmission by writing a byte to its SPI serial shift register. The register transmits the byte to the slave device through the MOSI pin, and the slave device also returns the contents of its shift register to the host through the MISO signal line. In this way, the contents of the two shift registers are exchanged. The write and read operations of the peripheral are completed synchronously, so SPI becomes a very effective serial communication protocol. The communication network structure block diagram of the SPI port is shown in Figure 1. In order to make the signal generator output a two-phase four-channel PWM wave with adjustable frequency, voltage and phase output, the DSP needs to output parameters to the CPLD circuit. The transmission of these four control parameters is realized in a small communication network. In this network, the SPI of DSP only performs write operations on the data output port, that is, output voltage control word, phase control word and frequency control word. Data flow: The host DSP transmits data to the CPLD. When transmitting data, the data is output on the MOSI pin, and the data is synchronously shifted and output under the action of the clock signal. Since there is no need for the slave to send any data back to the host, the host ends the transmission after the data transmission is completed. Since there is no response signal when the SPI port is working, and no check bit is required when sending data, the data transmission and reception of the master and slave devices must fully comply with the set SPI timing requirements, otherwise data transmission errors will occur.

2 Serial port SPI design based on CPLD

2.1 Shift Register Design

This design is a 12-bit SPI serial receiving port. The shift register in Figure 1 is composed of 12 D flip-flops and 1 counter to realize shift reception and serial-to-parallel conversion. During the transmission process, the shift register and counter are enabled first to start the transmission, and the counter starts counting at the same time. When the count reaches 16, the carry end outputs a high-level pulse with a pulse width to latch the data. The circuit is shown in Figure 2.

In order to ensure the correct timing in the experiment, the output timing of the enable signal and the counter carry pulse was measured, as shown in Figure 3 and Figure 4. The hexadecimal counter uses rising edge counting, and when the 16th rising edge arrives, it jumps to a high level to ensure the correct reception and latching of the data.

2.2 Latch Design

The working characteristics of the latch: when a high-level signal is input to the gate pin, the latch starts to latch the data on the bus; when the gate pin is at a low level, the latch does not work, that is, when the data on the bus changes, the output of the latch does not change. Since this design requires multiple parameter transmissions, the three data are distinguished from one bus by address selection, and the lower two bits of the transmission data are set as address selection bits. The address selection bits are converted from serial to parallel through the shift register and used as the two input ends of the three-input AND gate for address selection. Each time the 16-bit data shift is completed and the data is stable, under the action of the high level of the counter, the corresponding gate pin outputs a high level, and the data is latched into the corresponding latch. For example, when the lower two bits are set to "11", the DSP sends an 11-bit phase modulation signal to the PWM circuit; when the lower two bits are set to "01", the DSP sends a 10-bit signal to adjust the duty cycle of phase A to the PWM circuit; when the lower two bits are set to "10", the DSP sends a 10-bit signal to adjust the duty cycle of phase B to the PWM circuit. Therefore, a three-input AND gate can be designed in the circuit. When the 16-bit data transmission is completed, that is, when a high level is output on the corresponding gate pin, the data is stored in the corresponding latch, as shown in Figure 5.

2.3 Interface Configuration between DSP and LTC6903

Since the LTC6903 chip itself has an SPI interface, the corresponding SPI register needs to be set in the DSP program. LTC6903 uses rising edge reception, and the high bit is in front when receiving, so the DSP needs to be set to falling edge transmission, and the high bit is in front when transmitting. During the transmission process, the data changes on the falling edge of the pulse signal and the data is transmitted; the data is stable on the rising edge of the pulse signal, which is convenient for LTC6903 to latch the data. The transmission timing is shown in Figure 6. It can be seen from the figure that the data to be transmitted is the hexadecimal number 019A, the falling edge data changes, the rising edge data is stable, and 16 bits of data are transmitted, with 16 pulses. The experimental results show that the DSP configuration matches the working timing of the SPI interface of LTC6903.

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3 Development process of SPI in DSP

The characteristics of SPI port data transmission are: the presence or absence of the clock signal of the master device determines the start of data transmission. Once the clock signal is detected, the transmission starts, and the transmission ends when the clock signal is invalid. During this period, it is very important for the slave device to enable the start and stop status of the clock signal. The start and stop status of the clock signal of the SPI port of DSP56F801 is listed in Table 1. The CPOL and CPLA bits of the SPI control register set in the design are "11". SCLK is high when idle, and data changes during transmission occur on the falling edge and stabilize on the rising edge. As can be seen from Figure 2, the matching with the shift latch circuit in the CPLD is achieved, and the transmission is correct.

The SPI port protocol requires that the slave starts working before the master after the system is powered on and reset. If the slave starts working after the master, it is possible to lose part of the clock signal, so that the slave does not start receiving from the first bit of the data, causing the data stream to be out of sync. Hardware delay or software delay can be used to ensure that the slave works before the master. This design uses software delay to achieve data stream synchronization. This delay consists of two parts, one is the time delay of the DSP serial output data, and the other is the delay in the subsequent digital circuit. The specific calculation process of the delay is as follows: The clock signal used for data transmission is 2-divided by the bus clock. When the main frequency of the DSP is 60 MHz, the bus clock frequency is 30MHz. By dividing it by 2, it can be calculated that the period of SCLK is 66.6ns (the actual measured period is 78.2ns). In addition, through testing, it is found that the maximum delay of the PWM circuit is 23.6ns, the maximum delay of the latch is 7.6ns, and the maximum delay of the shift register is 3.0ns. From the above test of the delay of the CPLD digital circuit and the SCLK cycle, we can draw the following conclusion: Assuming the delay time of the PWM circuit is t1, the delay time of the latch is t2, the delay time of the shift register is t3, and the clock cycle of SCLK is Tc, during the SPI transmission process, the delay t of the entire circuit can be calculated as follows:

Since there is such a delay in digital circuit transmission, a certain delay needs to be added when writing DSP programs. The delay added in this experiment is 2μs, which can achieve reliable transmission.

4 Experimental Results

This design adopts a fully digital structure and is easy to implement with CPLD. With EPM7256 as the target chip, the correct data transmission is designed and implemented. When the hexadecimal parameters output by DSP56F801 are frequency word DBOE, phase word 0403, duty cycle word 04CE of phase A, and duty cycle word 04CD of phase B, the waveform output is shown in Figure 7 and Figure 8. Figure 7 shows the measured waveform of the output signal of phase A of the signal generator, and the signal duty cycle is adjusted to 20%; Figure 8 shows the measured waveform of the output signal 1 of phase A and the output signal l of phase B, and the phase difference of the two-phase signal is adjusted to the commonly used 90°. The experimental results show that the parameter transmission is correct and the waveform output is good.

Conclusion

SPI communication has the advantages of simple hardware connection and easy use, and is widely used. Taking measures combining hardware and software can ensure the synchronization of data flow in SPI communication and achieve reliable communication. This paper gives the design and implementation process of DSP multi-SPI port communication and discusses the key technical issues. The SPI multi-port communication method is based on CPLD, which is easy to transplant and easy to implement functional expansion. It can be widely used in various automation devices that use SPI communication.