Arbitrary waveform generator based on CPLD

Introduction

Arbitrary Wave Generator (hereinafter referred to as AWG) is widely used in communication systems, test systems and other aspects. This article uses the independently developed 150 MSPS (Million Sampling Per Second) 12-bit DAC (Digital Analog Converter) and 300MSPS 12-bit DAC to design an AWG based on CPLD technology. The waveform to be generated is set through the host computer software, and then the waveform data is downloaded to the AWG. Under the high-speed control circuit of the CPLD, the AWG sends the waveform data to a high-speed DAC for conversion to form the desired waveform. Let’s first analyze the hardware structure of AWG.
? The working process of
the hardware structure of the arbitrary waveform generator

AWG is to first receive the waveform digital signal sent from the host computer and store it in the SRAM, and then start the control circuit to take out the data from the SRAM and send it to the DAC for digital-to-analog conversion, and the converted analog signal is sent to the low Pass filter to form waveform. If the DAC works at a speed of 150MSPS, it can send data to the DAC at a frequency of 150MHz for conversion. The crystal oscillator input of the microcontroller generally works below 40MHz and cannot send data to the DAC at such a high speed, so consider using CPLD to build hardware control. circuit. The data is first transferred to the SRAM, and then under the control of the CPLD hardware control circuit, the data is taken from the SRAM and sent to the DAC for conversion at a frequency of 150MHz. Its architecture is shown in Figure 1. If you want to form a sinusoidal periodic signal, 4 points per cycle can be synthesized into a waveform, and a high-frequency signal of about 38MHz can be output at this time.

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Figure 1 AWG hardware structure

CPLD (Complex Programmable Logic Device, complex programmable logic device) is developed on the basis of traditional PAL and GAL. It has multiple working modes and obvious advantages such as high integration, high speed and high reliability. Features, it has a very wide range of applications in ultra-high-speed fields and real-time measurement and control. Compared with FPGA, CPLD is more suitable for I/O-intensive applications such as computer bus control, address decoding, complex state machines, timers/counters, and memory controllers. It does not require external configuration ROM and has predictable delays. Current CPLDs are generally based on E2PROM and Flash electrically erasable technology, which can achieve cyclic erasing and erasing. Altera's MAX7000 CPLD is equipped with a JTAG port and supports ISP programming. Programs designed with VHDL or Verilog HDL (Hardware Description Language, Hardware Description Language) use EDA tools to undergo behavioral simulation, functional simulation and timing simulation, then generate a netlist through a synthesis tool and download it to the target device to generate a hardware circuit.

In this device, the CPLD uses Altera's EPM7128AE [4], whose maximum operating frequency reaches 200MHz. The microcontroller adopts Atmel's AVR microcontroller AT90S8515[2]. Its main features are: enhanced RISC architecture CPU, 8K Flash, 512-byte EEPROM, 512-byte Internal SRAM, UART, SPI, wide voltage range: 2.7 -6.0V. SRAM uses 64K x 16 CY7C1021V.

The following analyzes the CPLD control circuit.

CPLD circuit design

CPLD is mainly responsible for fetching numbers from SRAM to DAC at a high speed (150MHz). Its core circuit is a 13-bit counter. The size of the waveform data file is 8Kbytes. If you want to expand the size of the waveform file, you can increase the address counter capacity of the CPLD as needed. The DAC control circuit constructed inside the CPLD is shown in Figure 2. Its control process is analyzed below.

PA[15:0] is connected to the two 8-bit parallel ports of AT90S8515; D[15:0] is connected to the SRAM data lines D0-D15; AD[12:0] is connected to the SRAM address lines A0-A12; DB[15: 0] Connect to D0-D11 of the DAC (not used for D12-D15); CLK_SEL selects the clock input mode of the counter; CLK_AVR is connected to an I/O terminal of the MCU, and the pulse signal is output on CLK_AVR as the clock of the counter through software programming; CLK_CPLD is connected to the 150MHz clock Signal; /WR and /WE are connected to the I/O terminal of the MCU.

When the PC downloads data, the control flow is as follows:
①CLK_SEL=0, select the software clock
②Reset the address counter
③MCU sends data to PA[15:0]
④/WR changes from 0 to 1, opens the data buffer from MCU to SRAM The device writes data
to SRAM ⑤ Give CLK_AVR a pulse to increase the counter by 1 to point to the next receiving address unit of SRAM.

When the data download is completed, CPLD is started to fetch data from SRAM to DAC. The control process is as follows:
①WE=1, open the buffer from SRAM to DAC.
②CLK_SEL=1, the input clock of the counter selects the 150MHz external clock,
③Reset the address counter, the address counter starts counting driven by the external high-speed clock, and the data is taken out from the SRAM and sent to the DAC for data conversion.

CPLD programming is carried out in the QuartusII5.0 environment. Quartus design input supports program input and graphical input of hardware description languages ​​such as AHDL, VHDL, Verilog HDL, and graphical input is used here. After completing the design input, compile, functional simulation, and timing simulation are performed in sequence. Figure 3 below is the timing simulation result of CPLD taking data to DAC for conversion. The operating frequency of the CPLD in the figure is 125MHz, and in actual operation, the highest operating frequency is 200MHz. As can be seen from the figure, every time a clock comes, the CPLD takes out a piece of data from the SRAM and sends it to the DAC for A/D conversion. Finally, the results are downloaded to the CPLD for internal operation.

Software design

AWG software is written using CodeVision AVR C [3]. AT90S8515 supports ISP (In System Programming). After the program is compiled, it is downloaded to AT90S8515 through the JTAG port. In order to cooperate with the use of this device, we designed the host computer software in the VB development environment. Its running interface is shown in Figure 4. Select the waveform to be generated in the software and then download it to the AWG.

The AWG and the PC use RS-232 serial communication. After powering on and running, wait for the PC to transmit the waveform. After receiving the waveform data, start the CPLD to take out the data from the SRAM and send it to the DAC for D/A conversion, and then form an output waveform through a low-pass filter.

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Figure 4.

Conclusion of

waveform data generation software . After the AWG and PC are connected through the RS232 serial port, run the PC software, select the waveform to be generated on the PC, and download the generated waveform data to the AWG. You can choose absolute phase shift keying with linear modulation technology. (BPSK), relative phase shift keying (DPSK), quadrature phase shift keying (QPSK), interleaved quadrature phase shift keying (OQPSK), π/4 offset differential phase shift keying (π/4-DQPSK) ), binary frequency shift keying (FSK) of constant envelope modulation, minimum frequency shift keying (MSK), Gaussian filtered minimum frequency shift keying (GMSK), M-phase phase shift keying of hybrid linear and constant envelope modulation techniques Control (MPSK), multi-ary quadrature amplitude modulation (QAM), multi-ary frequency shift keying (MFSK) and other waveforms, download them to the AWG to generate the desired waveforms. Figure 5 below is the 2FSK (Frequency Shift Key) waveform synthesized by the DAC operating at 125MHz.

Figure 5 2FSK waveform

References:
[1] Huang Zhengjin, Xu Jian, et al., Introduction and Application of CPLD System Design Technology, 2002, Beijing
[2] Atmel Corp., AT90S8515 datasheet, 2002
[3] Atmel Corp., CodeVision AVR C Compiler Reference ,?2002
[4]Altera Corp.,MAX7000 Programmable Logic Device Family Data sheet,November,2001