Design of an image acquisition and processing system for laser warning aircraft

Design of an image acquisition and processing system for laser warning aircraft

1 Introduction

Laser warning machine is a passive optoelectronic detection device, whose function is to detect the properties of target laser signals, such as wavelength, azimuth, etc. This system can complete the function of detecting and extracting laser wavelength information. In the laser wavelength measurement system, the time for the laser signal to be output from the CCD camera to the signal processor and the processing time of the processor are the two key factors for real-time monitoring of the laser wavelength. Even if a high-speed single-chip microcomputer is used, it is limited to its serial processing mode and long fetch time, and cannot meet the purpose of real-time measurement. Therefore, in order to achieve a response to the wavelength of the target laser signal within a few milliseconds, we can only hope for high-performance DSP devices or FPGA devices. In the warning system, the interface of the camera also puts forward requirements for the selection of devices: the acquisition device must support LVDS level, otherwise a level conversion chip must be added, which will inevitably bring delays in data transmission; in addition, when FFT is used for data processing, since FFT has the characteristics of repeatability and parallel processing in the algorithm, in order to achieve real-time processing, it is required to select a processor with parallel processing function. In the design, Xilinx's Sp3 series FPGA is selected as the control and processor. The benefits of using FPGA in this system are: (1) High-density FPGA can realize multiple sub-modules on a chip, effectively reducing the size of the laser warning receiver; (2) FPGA has a mature clock management system and a precise clock control system, which can achieve seamless connection between acquisition and processing, thereby improving system reliability; (3) FPGA supports multiple signal standards. In particular, in the alarm system, FPGA can set the interface to LVDS type, making the communication between FPGA and camera more direct, avoiding the related work of using level conversion chips in the past; (4) FPGA has parallel processing function, which can realize pipeline operation and reduce the time of FFT operation during signal processing.
2 Principle Overview
The camera transmits the detected laser signal to FPGA through the Cameralink interface. FPGA controls the timing generation to complete the following tasks: input clock signal to CCD; set CCD integration time through the trigger end; realize serial-to-parallel conversion of received data by STROBE signal of frequency doubling camera; transfer parallel data from FIFO to block RAM under the control of read enable. In order to improve the response time of the laser warning machine, the system makes full use of the function of FPGA pipeline operation. Two 1024-unit data storage devices are provided at the data receiving end to work alternately. The storage intervals are switched by setting flags in the software. During data storage and data processing, when FPGA uses area 1 to collect the i-th frame of data, area 2 processes the i-1 frame of data at the same time. When both are completed at the same time, area 2 is used to collect the i+1 frame of data, and area 1 processes the i-th frame of data at the same time. In this way, the work is alternated to form a pipeline operation. Due to the difference in camera acquisition rate and block RAM write time, two FIFOs are generated by IP core inside FPGA to achieve buffering for the reception of two data channels to achieve synchronization. The write and read timing and address generator of block RAM are written in VHDL language. Data processing is carried out by reading the data in RAM one by one under the synchronization of the clock, and a 10-stage pipeline base-2 algorithm is used to realize the 1024-point fast Fourier transform to obtain the spectral characteristics of the input laser signal. The acquisition and processing system block diagram of the laser warning machine is shown in Figure 1.

3 System Design
The whole system consists of two parts: data acquisition module and data processing module.
3.1 CCD camera data acquisition module The
design uses AViiVA M2 CL camera of ATMEl company. The camera adopts Cameralink interface. The core of Cameralink technology is a high-speed data transmission method proposed by NS (National Semiconductor) in the United States—Channel Link technology. This technology is mainly used for high-speed transmission of digital image data. It adopts LVDS signal mode. The LVDS low voltage swing differential mode has the advantages of small cross interference and EMI interference during high-speed data transmission. The maximum transmission rate can reach 2.38Gb/s. The interface of the camera is defined as: four pairs of LVDS lines, used for FPGA to control the camera; two pairs of LVDS lines, used for communication between the camera and FPGA, with a speed of up to 9600 baud rate; four pairs of LVDS lines, used to output data and data bit synchronization and frame synchronization signals. The XC3S400 FPGA is selected. It has rich interface standards, especially supports LVDS signal standards, and can be directly connected to the camera with Cameralink interface. The camera working mode is set by FPGA based on RS-232 protocol serial communication, using full-duplex, asynchronous serial mode without handshake signal, baud rate is fixed at 9600Hz, each frame of data consists of a start bit, 8 data bits, and a stop bit. The camera's integration time and output gain can be set to different values ​​as needed. The trigger mode of the camera is triggered by the FPGA externally, so that the FPGA and the camera share the same global clock.

During the data acquisition process, the synchronization signal for data transmission is generated by the STROBE pin. When the data is fully stored in one data area, the LVAL pin is used to notify the FPGA to transfer to another data storage area. Figure 2 shows the timing diagram of data acquisition. Among them, CLK_IN is obtained by frequency multiplication by the FPGA's core digital clock management module DCM. In terms of clock control and management, DCM is more powerful and more flexible than DLL. The main functions of DCM include eliminating clock delay, frequency synthesis and clock phase adjustment. In this design, the input clock STROBE is multiplied by 8 to achieve the latch output of data one-to-eight serial-to-parallel conversion.

The design of high-speed acquisition program mainly includes three parts: interface matching, acquisition state machine and data storage. In interface matching, since the input and output of LVDS are internally matched, the LVDS can be directly connected. In FPGA, the differential input clock buffer (IBUFDS), the differential input global clock buffer (IBUFGDS) and the differential output clock buffer (OBUFDS) need to be instantiated.
Part of the FPGA code is as follows:
component IBUFDS - - Differential input clock buffer (IBUFDS)
port (O: out STD_ULOGIC;
I: in STD_ULOGIC;
IB: in STD_ULOGIC);
end component;
IBUFDS_INSTANCE_NAME: IBUFDS
port map (O=>user_O,I=> user_I,IB =>user_IB);
3.2 Data processing module
Spartan3 series FPGA has abundant multiplier resources. Without using any optimization algorithm, each butterfly operation requires 4 real multipliers. Therefore, in FPGA, each butterfly operation can be completed in one clock cycle with 4 multipliers. Abundant RAM resources facilitate the implementation of data pipeline operation, that is, different storage areas can be opened for input, output data and intermediate variables. For example, when calculating the i-th group of data, the i-1-th group of calculation results is being output, and the i+1-th group of data is being input.
Since complex numbers are inevitably generated in FFT operations, the data input port of the FFT converter is divided into real and imaginary numbers at the beginning of the design for the convenience of calculation. The 1024-point complex FFT operation is divided into 10 levels according to the base-2 frequency extraction operation. Each level includes 1 dual-port RAM, 1 address generator, 1 ROM for storing the rotation factor table, 1 butterfly operation unit, and 2 selection buffer units. In order to simplify the address unit circuit, the real and imaginary parts of the complex data are combined into one data and stored in the RAM. Since the dual-port RAM is used, when the data in a storage unit is read out for operation, the storage unit can store the data from the previous level. Therefore, the FFT of this structure can be pipelined and can perform real-time and continuous operations on signal samples. The purpose of the selection buffer is to align the data, split the 2 complex data output by the RAM into 4 real data and input them into the butterfly operation unit. The data after the butterfly operation enters the selection buffer and is combined into 2 complex data outputs.

It can be seen that the real number multiplication required for complex multiplication is changed from 4 to 3, and the factor can be stored in ROM as a constant, so that complex multiplication can be completed with only 3 real number multiplications and 3 real number additions. The schematic diagram of the butterfly converter generated by the above algorithm after synthesis is shown in Figure 3. In the schematic diagram, clk is the clock input pin; X_re, X_im, Y_re, Y_im are the real and imaginary parts of the complex numbers X and Y respectively; Cin represents; cms and cps represent and respectively; out1_re, out1_im, out2_re, out2_im represent the real and imaginary parts of the two output data after the butterfly transformation.

The address generation and control unit controls the storage, read and write timing of the entire data involved in the FFT operation, and is an important part of the FFT operator. The address generation and control unit will generate the read and write address of the input data of each order operation unit, the read and write of the memory, the enable control signal, and the read address of the rotation factor coefficient, and send the paired data and the rotation factor coefficient to the butterfly operation unit in sequence, so as to realize each order of butterfly operation. The design method of the address generation and control unit is mainly designed using a finite state machine. The operation process of each order operation unit is divided into different states, and different data addresses and control signals are output in different states.
Table 1 lists the situation of calculating a frame of 1024-point FFT occupying FPGA internal resources. After post-simulation timing analysis, the laser warning system only needs 110μs to complete a frame of 1024-point FFT when the system clock is 50MHz, and only 230μs is needed to add data loading time and data reading time, which meets the requirements of real-time processing. As can be seen from the table, after the FFT submodule is completed, there are still a lot of FPGA resources available, so the remaining resources can be used for the acquisition module, thereby completing multiple functions on one chip and effectively reducing the size of the laser warning machine.

The spectrum of the input signal of FPGA simulated by Matlab before signal processing is shown in Figure 4. It can be seen that the wavelength peak of the laser signal is around 523nm. After the data is FFTed in FPGA, the spectrum result obtained after the data is output in reverse order is shown in Figure 5. By comparing the two figures, it can be seen that the FPGA output is basically the same as the Matlab simulation result, thus verifying the correctness of the warning system.



4 Summary
This paper introduces the design of CCD camera signal acquisition and fast processing system equipment developed for laser warning machine to detect the wavelength of target laser. The system uses FPGA to realize the acquisition and processing of the output data of Atmel's AViiVA M2 CL linear array CCD camera. The circuit is simple and reliable, and it fully utilizes the characteristics of FPGA supporting multiple signal standards, supporting pipeline operation mode, and built-in block memory.
The author's innovation in this paper: In terms of circuit design: it gets rid of the previous practice of Cameralink interface cameras that must add a level conversion chip between the camera and the processor when communicating with the signal processor, and fully utilizes the advantage of FPGA supporting LVDS level, thereby reducing the circuit volume and complexity of the warning system and improving the reliability of the system in hardware. In terms of program design: make full use of the internal RAM resources of FPGA, use FIFO memory in many places, and use pipeline operation as a means to shorten the system response time.