Design of Gbps wireless communication base station based on Virtex5

introduction

As 3G mobile communications represented by TD-SCDMA have entered full commercial deployment, the LTE standard has been basically completed. Huawei and Ericsson have successfully achieved a field demonstration of the LTE standard[1]. The research and development of the next generation of mobile communication technologies, standards and systems based on LTE-A and IMT-Advanced has also begun.

The International Telecommunication Union (ITU) has officially named the future mobile communication technology after 3G IMT-Advanced. At the 2007 World Radio Conference, it allocated new frequency bands for it and began soliciting standard proposals in 2008. China has also started preparations for soliciting technical proposals from the ITU through the IMT-Advanced Promotion Group [2]. It has proposed that domestic technical proposals should have the characteristics of high spectrum efficiency and low system latency. The main technical indicators should be: variable system bandwidth of 5-100MHz; support for a peak rate of 1Gbps in fixed and low-speed mobile situations, and support for 100Mbps in high-speed mobile situations; a maximum of 8 antennas on the base station side and a maximum of 4 antennas on the terminal side; and support for a maximum mobile speed of 500km/h.

With the progress of technical research and proposal work, the research and development of base station systems has also begun. This research work is based on the national "863" plan Gbps wireless transmission key technology and test system research and development project, and develops a new mobile communication base station prototype that can verify related technologies and meet standard technical indicators for future mobile communication standards such as LTE-A and IMT-Advanced.

Algorithm link design for Gbps wireless communication systems

In order to meet the needs of future mobile communication standards [3], Gbps systems use high-performance physical layer transmission technologies such as time division duplex (TDD), multiple antennas (MIMO), space-time coding, orthogonal frequency division multiplexing (OFDM), high-order modulation and LDPC coding on the algorithm link to achieve the high data rate service transmission and high spectrum efficiency required by Gbps systems. The multiple access method based on frequency division and time division can flexibly allocate wireless resources in a multi-antenna environment, while taking into account real-time voice transmission and meeting the needs of packet data transmission to the greatest extent.

Specifically, the Gbps system uses the 3.4GHz frequency band, with an actual bandwidth of 100MHz. The mobile station uses 2 transmit and 4 receive antennas, and the base station uses 4 transmit and 8 receive antennas. The number of OFDM subcarriers is 2048 subcarriers, which is effectively 1*subcarrier. Figure 1 is a schematic diagram of the algorithm link of the Gbps wireless transmission system.

Figure 1 Gbps wireless transmission system algorithm link

Design and Implementation Considerations of Gbps Base Station Systems

Mobile communication base stations often have multiple standards such as GSM and TD-SCDMA at the same site. There is an increasing coexistence of multiple standards. Base station research and development should focus on reducing construction, operation and maintenance, and upgrade costs. In this regard, Gbps wireless communication base stations should adopt a reconfigurable method to support Gbps wireless transmission while being compatible with future LTE-A and IMT-Advanced standards to achieve smooth evolution.

From the perspective of implementation technology, programmable processing devices are required to implement signal processing algorithms and support reconfiguration. The programmable processors widely used in modern base station systems are mainly DSP and FPGA. Although the working clock frequency of high-end multi-core DSP has been increased to 1.2GHz and is widely used in TD-SCDMA base stations, it still cannot meet the signal processing complexity and real-time requirements of synchronization, MIMO, LDPC and other algorithms in Gbps systems. Therefore, Gbps projects need to use large-capacity, high-performance FPGAs as the carrier platform for complex algorithms.

From the perspective of the interconnection and data transmission mechanism of the base station system, interconnection connects all wireless interfaces, network interfaces and computing resources, and transmits data representing computing tasks, which is the key element to make the base station system operate as a whole and in a coordinated manner. Since the MIMO algorithm requires the transmission of multi-antenna input data to multi-baseband processing chips, a switched interconnection network and packet data transmission mechanism should be adopted to better meet the needs of MIMO, parallel processing, dynamic reconfiguration, dynamic scheduling of computing resources, etc. in future base station systems.

Taking into account the above design and implementation considerations and after comprehensive research and investigation, the Gbps project decided to use Xilinx's Virtex-5 series FPGA architecture hardware system platform [4] to carry complex signal processing algorithms, use Serial RapidIO [5] technology as a high-performance interconnect between boards, and use Gigabit Ethernet (GE) to connect business servers and LMT computers.

Introduction to Virtex-5 FPGA

The Virtex-5 series FPGA is the 65nm platform FPGA first released and mass-produced by Xilinx. It currently includes multiple sub-series such as LX, LXT, SXT, FXT and TXT for different applications.

The Virtex-5 series FPGA can achieve a maximum operating clock of 550MHz, with a total number of logic units of up to 330,000. It provides flexible embedded Block RAM of up to 11.6 Mbit, which can effectively store and buffer various computing data. Up to 640 enhanced embedded DSP48E slice blocks can meet the needs of high-performance DSP algorithm acceleration and achieve 352 GMACs performance. Virtex-5 FXT series FPGA provides up to two standard PowerPC 440 processor modules, each of which can provide 1,100 DMIPS performance at a clock frequency of 550 MHz. Using the PowerPC 440 embedded processor module, complex control and communication protocol processing in Gbps base stations can be quickly and easily implemented.

The Virtex-5 series FPGA integrates high-performance transceivers of 100Mbps-6.5Gbps, and can realize high-performance data exchange interconnection between chips and boards with the serial RapidIO logic layer module implemented by internal FPGA programming. It integrates 10/100/1000Mbps Ethernet MAC hard core that complies with the IEEE 802.3 standard, connects to external GE PHY or directly uses the GTP/GTX of the FPGA itself to realize high-performance Gigabit Ethernet interface.

Algorithm resource requirements and FPGA model determination

By analyzing the different implementation characteristics of each algorithm in the Gbps algorithm link and estimating the amount of computation and the main resources used, the required FPGA can be determined. Table 1 shows the results of resource requirement estimation and FPGA selection, and Table 2 is a summary of the internal resources of the target FPGA.

Table 1 Gbps wireless communication base station system algorithm link requirements for FPGA resources

Among them, the LDPC encoding at the transmitter and the LDPC decoding at the receiver are mainly logical operations, which do not require multiplier resources, so they are implemented using the LXT in Virtex-5. Algorithms such as synchronization, FFT/IFFT, modulation/demodulation, and space-time decoding require a large number of multiplier resources, and are implemented using the SXT series that integrates a large number of DSP48E modules. MAC processing and network interfaces are implemented using two PowerPC440 processors in the FXT series FPGA and an embedded Gigabit Ethernet hard core. The use of the PowerPC processor in the FPGA can greatly reduce the complexity of external circuit design, reduce the complexity of data exchange between the physical layer and the MAC layer, reduce system transmission delay, and use the PowerPC processor application processing acceleration unit (APU) to implement customized instructions, greatly improving the efficiency of MAC processing.

Table 2 Virtex-5 FPGA resources and quantity statistics used in base stations

Gbps wireless communication base station designed based on Virtex-5 FPGA

FIG2 is a block diagram of the hardware implementation of the designed Gbps wireless communication base station baseband processing system.

Figure 2 Hardware block diagram of Gbps wireless communication base station baseband processing system

According to the results of the algorithm requirements analysis, the Gbps base station system was finally built around 9 LX155Ts, 17 SX95Ts, and 1 FX100T FPGA. Among them, 4 SX95Ts are used to realize the reception synchronization/de-framing/de-slotting of 8 antennas, and each FPGA processes 2 antennas; 4 SX95Ts are used to complete the IFFT and channel estimation of OFDM reception of all 8 antennas; 8 SX95Ts are used to complete the MIMO space-time decoding processing of 4 transmissions and 8 receptions, and 8 LX155Ts are used to complete demodulation, deinterleaving and LDPC decoding; the PowerPC440 processor in the FX100T completes the MAC layer data transmission and reception processing; and 1 LX155T completes the LDPC coding of transmission. All FPGAs are packaged in FF1136. Since Virtex-5 FPGA adopts pin-compatible design, SXT, LXT and FXT can be directly replaced, which reduces the workload of PCB design and increases the flexibility of system application.

The ADC uses TI's 11-bit ADS62P15, the DAC uses ADI's AD9779A, and the ADC, DAC sampling clock and FPGA working clock frequency are 122.88MHz.

The interconnection design of the Gbps base station system is as follows: differential LVDS connection is used between ADC and synchronization FPGA; 48 pairs of differential LVDS connection are directly used between each group of synchronization/de-framing/de-slotting and channel estimation/IFFT FPGAs and space-time decoding and LDPC decoding FPGAs; the remaining FPGAs are interconnected using a 14-port Serial RapdIO switch. The structure and interface of the Gbps base station system are built with Advanced Telecommunications Computing Architecture (ATCA) and Serial RapidIO. The modular structure and switch-based interconnection make it easy to increase the number of baseband processing boards or expand new functional modules.

in conclusion

Future mobile communication systems such as LTE and IMT-Advanced need to support a large number of broadband users and extremely high air interface rates, use complex communication signal processing algorithms such as MIMO, OFDM, and LDPC, and have dynamic reconfiguration and dynamic scheduling of computing resources, which puts extremely high demands on the computing processing and interconnection of base stations. The Gpbs wireless communication base station designed with a single-platform multi-series Virtex-5 series FPGA as the core adopts a data transmission mechanism based on switching interconnection and packetization, which can verify various algorithms and technologies used in future wireless communications and realize Gbps wireless transmission communications.