Design of DDS Signal Generator Based on SOPC

Abstract: Direct digital frequency synthesis technology is a new signal generation method and the development direction of modern signal sources. The system consists of FPGA control module, keyboard, LED display, and combines the structure and principle of DDS. SOPC and DDS technology are used to design a multi-waveform signal generator with frequency setting function. Taking the core device EP2C35 of Altera's CycloneⅡ as an example, NIOS ⅡCPU realizes the output display function of arbitrary stepping and different waveforms by reading the value of the button.

0 Introduction

Direct Digital Frequency Synthesis (DDS) is a new type of frequency synthesis technology. It improves the frequency stability and accuracy of the signal generator to the same level as the reference frequency, and can perform fine frequency adjustment in a wide frequency range. In the field of modern communications, DDS is widely used. The common method to implement DDS is to use a dedicated DDS chip and an independent MCU for the control part. The integration and scalability of the system designed in this way are not satisfactory. With the introduction of large-scale field programmable gate arrays and the continuous development of SOPC, designers can design various systems on the embedded soft-core processor of FPGA to meet user needs. This paper designs a direct digital frequency synthesizer based on SOPC technology, selects Altera's new generation FPGA (Cyclone Ⅱ) as the core, uses the logic unit of FPGA to realize digital logic functions such as phase accumulation, puts sine table, square wave table, triangle wave table, and sawtooth wave table in ROM, and uses soft-core CPU for control to realize frequency, phase, waveform selection, etc. This can greatly reduce the number of processor peripheral expansion circuits, improve the system's stability and anti-interference capabilities, and save internal resources.

1 System design

The system adopts SOPC design scheme. The overall system block diagram is shown in Figure 1. It consists of frequency preset circuit, waveform selection, waveform frequency control, accumulator, memory for storing waveform data, D/A conversion circuit, and filter circuit. The accumulator module is composed of a 10-bit adder and a 10-bit register cascaded. The data of sine wave, square wave, triangle wave, and sawtooth wave are placed in the waveform memory.

Figure 1 Overall system block diagram

1.1 Basic working principle of DDS

The basic principle of DDS is to use the sampling theorem to generate waveforms through table lookup. A complete DDS structure diagram is shown in Figure 2.

Figure 2 DDS structure diagram

The phase accumulator accumulates once with the frequency control word K at each rising edge of the clock. When the accumulator counts more than 2N, the phase accumulator is equivalent to performing a modulo operation. In each clock cycle, according to the address sent to the ROM, the waveform data corresponding to the address in the ROM is taken out. After reading the data in the ROM, the digital quantity is converted into analog quantity through the D/A converter, and a smooth waveform can be output through the low-pass filter circuit.

Assuming the carrier frequency is fc, its time domain expression is:

Its phase expression is:

The relationship between the output frequency f 0 and the clock frequency f clk satisfies:

When K = 1, DDS has the minimum frequency output, so the step size of DDS is f clk / 2N, and the maximum output frequency is f clk / 2. In this design, N is set to 10 bits, M is set to 12 bits, and the phase accumulator accumulates with a step size of K under the control of the clock, outputs N-bit binary code, and uses it as the address of the waveform ROM to address the waveform memory ROM. After the data output by the waveform memory ROM is converted into a step wave by D/A and smoothed by a low-pass filter, the synthesized waveform is obtained. The shape of the synthesized waveform depends on the waveform selection and the data in the ROM.

1.2 D/A Converter

The output from the DDS core is a digital signal, which needs to be converted into an analog signal for easy observation. DAC has two types of output: voltage and current. The output signal cannot be truly continuously variable, but is based on its absolute resolution as the minimum unit, so its output is actually a step analog signal, so the D/A output signal needs to be smoothed through a low-pass filter to obtain a pure analog signal. In this design, a D/A converter model AD9742 is used. AD9742 is a 12-bit, low-power D/A converter with a conversion speed of up to 100 Mb/s.

1.3 SOPC-based hardware architecture

System development includes hardware and software, and the hardware part is built by SOPC development tools. SOPC Builder generates NIOS embedded processors. NIOS embedded processor development tools allow users to configure multiple CPUs, add peripheral circuits to the standard library, and also allow users to customize peripherals and comprehensively process customized systems, making the design more flexible.

After opening SOPC Builder, add CPU, PIO input (10 buttons for frequency word input, 1 button for confirmation, 4 buttons for waveform selection), memory (FLASH, SRAM and SDRAM), PIO output (10 bits for ROM address, 2 bits for ROM block selection, 7 bits for LED segment code, 1 bit for LED selection) and timer. The hardware architecture diagram after all components are added is shown in Figure 3.

Figure 3 SOPC hardware architecture

After SOPC Builder is generated, the generated CPU module can be added in Quartus software, and the DDS module is written in VHDL language. The DDS module diagram is shown in Figure 4. The ROM size is 12 1 024, and a total of 4 ROMs are set to store sine waves, square waves, triangle waves, and sawtooth waves respectively. The waveform data is calculated by Matlab software and the data is stored in .mif file format. The output of the accumulator is the address of the waveform memory, and after the phase amplitude conversion of the waveform, it is used as the amplitude of the output waveform. The 10-bit addressing ROM is equivalent to discretizing a signal of one cycle to form a sequence with 1 024 sample values. The address generated by the accumulator reads the data in different memories through the address allocation of the waveform, and then the read data is converted into analog signal output through the D/A converter.

2 Software Design

NIOS complete development environment is the interface between NIOS processor and user. All software development tasks can be completed using NIOS IDE, including program editing, compiling and debugging. Hardware abstraction layer (HAL) supports general I/O devices and can access hardware by writing standard C programs. HAL reduces the access to hardware registers and directly communicates or controls peripheral devices. Different peripheral hardware requires different levels of HAL support and needs to run HAL software drivers. DDS system control is implemented in standard C language under NIOS IDE environment. The entire design is completed through the steps of writing code, compiling, linking, debugging and downloading.

After opening the IDE development environment, the first step is to create a new project. After adding the .ptf generated by SOPC Builder, the system automatically generates the corresponding header file according to the address allocation of the hardware. The header file defines the base address of each component. When the SOPC system changes, the IDE will recompile the HAL when the user compiles and runs the application. The flowchart of the entire software writing is shown in Figure 5.

Figure 5 Software Flowchart

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3 System debugging process and results
The system clock is 50 MHz. When the waveform selection key is selected as sine wave and the frequency word is set to 5, the digital tube displays 5. After pressing the confirmation key, the digital tube displays "-". Through the oscilloscope, the output waveform can be observed as shown in Figure 6. The horizontal axis is the time frame and the vertical axis is the amplitude. When the waveform selection key is selected as square wave and the frequency word is set to 10, the digital tube first displays 1 and then 0. After pressing the confirmation key, the digital tube displays "-". The waveform observed on the oscilloscope is shown in Figure 7. According to the above operation process, the waveforms of the triangle wave and sawtooth wave are shown in Figure 8 and Figure 9 respectively.

Figure 6 Sine wave waveform

Figure 7 Square wave waveform

Figure 8 Triangle wave waveform

Figure 9 Sawtooth Waveform

4 Conclusion

This paper designs the preset of frequency words and the selection of waveforms, which are input through the keyboard, so that any frequency waveform within the specified range can be obtained, which can well meet the situation of variable frequency signals and is highly practical. The waveform debugged by the experiment is clear and has little interference. The SOPC method is used to make the design very flexible. This design only realizes the input of waveforms of any frequency, and it is also necessary to realize phase accumulation to make the design more perfect.