Design and implementation of high-speed data acquisition system based on CPLD and embedded system

The high-speed data acquisition system consists of a high-speed ADC , CPLD , FIFO and an embedded system . The system structure is shown in Figure 1.

2.1 Embedded Operating System—Linux

Linux as an embedded operating system has the following advantages:

(1) Applicable to a variety of hardware platforms; (2) Open source code; (3) Microkernel directly provides network support; (4) High modularity makes adding components very simple.

2.2 Hardware Design

The entire data acquisition board adopts a double-layer design. The upper layer is the core board of the embedded system, including the basic system configurations such as the embedded system CPU, FLASH and SDRAM. The control bus and data bus of MPC860 communicate with the chips of the expansion board below through the 100-line × 3 interface socket of the core board. The hardware structure block diagram is shown in Figure 2.

The CPU of the embedded system uses Motorola's MPC860 chip. It integrates a microprocessor and some common peripheral components in the control field, and is particularly suitable for Internet and data communication. The MPC860 Power QUICC communication processor can provide 2 to 4 serial communication controllers, data cache, and various levels of network protocol support according to different user requirements. The processor is designed for broadband access devices such as routers, hubs, switches and gateways.

2.2.2 System Memory

The system memory consists of three parts. MPC860 integrates 4KB data cache inside, and Flash and SDRAM are extended outside the chip. Flash is 2 pieces of Am29LV160D, with a total capacity of 4MB×8bit, used to store ppcboot.bin and linux.bin files. SDRAM uses 2 pieces of K4S641632F, with a total capacity of 16MB×8bit.

2.2.3 General peripherals

The four serial communication controllers (SCC) of MPC860 support standard protocols such as Ethernet, HDLC/SDLC, HDLC bus (for realizing HDLC-based LAN), AppleTalk, UART, transparent bitstream transmission, transparent frame-based transmission (CRC optional), and asynchronous HDLC supporting PPP (Point to Point Protocol). Only a few peripheral chips are needed to realize the serial port and USB Slave interface. MPC860 can easily realize a 10BASET Ethernet interface by expanding an LXT905PC.

2.2.4 Embedded System Debugging

The MPC860 processor supports BDM (background debugging mode), which can complete the most basic debugging functions such as board hardware detection, downloading, running, burning FLASH, kernel debugging, single-step debugging, etc. In background debugging mode, registers and system memory can be accessed by sending commands to the CPU.

In addition, during debugging, you can also use Motorola's Power TAP Pro emulator and Code Warrior IDE for PowerPC compilation environment to develop and debug applications under Windows.

2.2.5A/D conversion and CPLD circuit

The device used for A/D sampling is ADC08200, with an accuracy of 8 bits and a sampling frequency ranging from 20MSps to 200MSps. The A/D sampling frequency in this circuit is 100MSps. The CPLD chip uses EPM3128ATC144-5, which has 128 macro units, can provide 2500 logic gates, and the upper limit of the counting frequency is 192.3MHz. The A/D sampling clock is provided by the CPLD. The crystal oscillator frequency is 100MHz, which is directly connected to the CPLD, and the CPLD generates other signals for the accumulation circuit.

2.2.6 Programming and debugging of CPLD devices

The CPLD device is programmed in VHDL language. After the program is logically synthesized (the logic synthesis software is Altera's QuartusⅡ 4.0), the *.pof file generated by the logic synthesis can be burned into the CPLD device through the JTAG (Joint Test Action Group) interface using a download line, and then the chip function can be tested.

2.2.7 FIFO data buffer circuit

As can be seen from Figure 1, the system contains two levels of FIFO. The first level FIFO chip uses a CY7C4251, with a capacity of 8KB×9bit and an operating frequency of 100MHz. The second level FIFO uses two CY7C4255 chips in parallel, with a capacity of 8KB×36bit, but in fact only 24bit data width is used, because 8bit A/D conversion data is accumulated 10,000 times, and 24bit can meet the functional requirements of the system.

2.3 Software Development

The software programming of the data acquisition system includes two parts: one is the programming of the MPC860 embedded system; the other is the programming of the CPLD. For the programming mode of the CPLD, see 2.2.6. Here we only introduce the software development mode of the embedded system.

This system uses cross-compilation to develop and debug Linux applications. The application is first debugged on the host machine and then ported to the target board. This mode is suitable for large and complex applications. The advantage is that the program debugging is convenient, but the porting requires some work. The development process is shown in Figure 3.