Design of radar/video data acquisition and playback system based on FPGA

0 Introduction
With the rapid development of science and technology, in the fields of military, aerospace, test and measurement, people have put forward higher requirements for the sampling accuracy, sampling rate and storage capacity of data acquisition systems. Traditional acquisition devices are inconvenient to use, and their limitations are very obvious. Obviously, they can no longer meet the needs of modern technological development. At present, with the advancement of integrated circuit technology, large-scale and ultra-large-scale programmable logic devices are widely used in actual system design. Due to its advantages of high integration, low power consumption, flexible design, high efficiency, and user-programmable characteristics, the device can greatly shorten the system design cycle, reduce design costs, and reduce risk investment. In addition, some devices also have the ability to be online programmable.
Here, a radar/video data acquisition and recording system is introduced. Its core technology is to use a high-speed programmable logic gate array FPGA to perform high-speed real-time acquisition of radar target echoes, and record the continuously acquired signal data on the computer hard disk for subsequent data processing needs. The characteristics of this system are: miniaturization, easy to carry, convenient connection, simple operation, long recording time, high sampling rate, high data transmission rate, large dynamic range (12-bit A/D resolution), and the use of orthogonal dual-channel acquisition method, which fully meets the needs of high-speed and large-capacity radar signal acquisition and recording.

1 System composition and working principle
The system is mainly composed of a computer and system acquisition hardware. The system acquisition hardware consists of a baseboard with dual-channel high-speed A/D and USB interface circuits and a core board with FPGA. The workflow of the radar data acquisition and recording system is shown in Figure 1.

The system uses a desktop PC as the main acquisition control device. The radar/video echo signal is converted into digital by the A/D converter, and then the core acquisition module controlled by the FPGA completes the data acquisition and quantification. The acquisition module can control the acquisition of radar echo signals according to the clock and synchronous trigger signals from the radar system, and then send the collected data to the USB through the buffer module. The USB interface packages the data and transmits it to the hard disk of the desktop computer for display and processing.
The data exchange between the FPGA and the host computer is an important part of realizing the system function. On the one hand, after completing the extraction and buffering of the collected data, the FPGA uses the high-speed USB 2.0 transmission method to transmit the data to the host computer in real time, so that the data processing can be carried out sequentially; on the other hand, some parameters of the data acquisition module are set by the host computer control panel and transmitted to the FP-GA via the bus.

2 Hardware circuit board design
In this system, the FPGA core board is responsible for data storage and data transmission control, and is the most critical part of this system. Considering system resources and FPGA price, it is more appropriate to choose Xi-linx's Spartan-Ⅱ series XC2S200 chip, and the power conversion chip LT1764 provides a stable power supply voltage for the FPGA. Its minimum system block diagram is shown in Figure 2.

XC2S200 is one of the Spartan-Ⅱ series FPGA products with better cost performance. It has a mature Virtex-E architecture, a core voltage of 1.8 V, a system performance of 200 MHz, a system gate count of 200,000 system gates, and an appropriate amount of block RAM (Block-RAM) inside. The chip supports a variety of interface standards. This system uses ADI's AD9224 as the A/D conversion chip to complete the dual-channel A/D sampling function. Its sampling frequency is 40 MHz, the number of bits used is 12 bits, and the chip integrates a high-performance sampling and holding amplifier and a reference voltage source. It has the logic function of correcting erroneous outputs, and accurately provides 12-bit output data at a sampling rate of 40 MSPS, ensuring that there is no missing code within the fully operational temperature range.
High-speed data acquisition speed is the standard to ensure data acquisition accuracy, but it is often not necessary to process data at the same speed, otherwise the hardware requirements are too high and the cost is also high. Here, a combination of synchronous FIFO, SRAM, and asynchronous FIFO is used to achieve buffering of collected data. At the same time, since the data transmission speed is greater than the sampling speed of AD, it ensures that the collected data is not missed during transmission.

3 Software Design
3.1 FPGA Program Design
This system adopts a design method that combines synchronous FIFO A, asynchronous FIFO B and buffer SRAM to form the data buffer module of this system. The detailed design process of the entire system is shown in Figure 3.

3.1.1 Data acquisition module design
In radar signal acquisition technology, acquisition timing control and real-time data transmission are the key and the technical difficulty. In order to ensure the continuity of acquisition, the design adopts the buffer technology of FPGA internal dual FIFO, external dedicated buffer chip technology and computer public buffer ring storage technology. The detailed software design process of this module is shown in Figure 4.
3.1.2 Data buffer module design
The data buffer module designs synchronous FIFO A and asynchronous FIFO B. One end of FIFO A receives A/D conversion data, and the other end transmits data to external SRAM; one end of FIFO B receives SRAM data, and the other end transmits data to the FIFO of USB microcontroller.
3.1.3 Frequency measurement module design
The measurement accuracy of the frequency meter based on the traditional frequency measurement principle will decrease as the frequency of the measured signal decreases, which has great limitations in practical use. The equal-precision frequency meter not only has high measurement accuracy, but also can maintain constant measurement accuracy in the entire frequency range. Considering comprehensively, this system adopts the measurement method of equal-precision frequency meter. Its basic flow chart is shown in Figure 5.

3.1.4 Design of voltage measurement module
After the collected signal is quantized and encoded by the A/D converter, the signal amplitude value can be calculated based on the quantized result. At the same time, considering that the collected signals, especially sine waves, triangle waves and other signals, will jitter during measurement, the method of combining averaging and signal smoothing is adopted to improve the accuracy of voltage measurement when measuring voltage, and the design realizes the measurement of peak-to-peak value and average value of the signal.
3.2 Application design
In design, after the USB driver is installed, the application calls the thread to obtain the valid handle of the device, and then it can communicate with WDM. Definition of interface data format We use the form of structured data packet. First, we design a C language structure, arrange the parameters to be communicated in the same order as the VHDL language, and then set the data packet format for these parameters on the USB communication protocol. When designing the storage problem of collected data, we call the thread to store the transmitted data array in the data format of "*.dat". When playing back and displaying, the data is read from "*.dat" to the predefined array for calling. The design process of the entire application is shown in Figure 6.
The main task of designing a virtual instrument is to write application software. Visual C++ is used to design the control panel. Considering the setting of signal parameters, the panel is divided into two parts: the acquisition parameter setting part and the display control part. The main function of the former is to pass the parameters to the hardware core processing part. The main function of the latter is to set the display parameters of the NTGraph control on the panel. The application control and display panel is shown in Figure 7.

4 System debugging and testing
After completing the hardware design and software design of the system, comprehensive debugging and testing are required. Through debugging, the program code is continuously optimized, and the problems in the program are corrected and modified in time, so that the performance of the system can be improved and the working state is more stable. During the test, the parameters of the components in the circuit can be corrected to avoid the gap between the theoretical analysis and the actual state causing the system parameters to fail to meet the requirements. At present, this system can realize the actual field data collection of various types of radars. Figures 8 and 9 are the single-channel intermediate frequency (without pulse compression processing) and dual-channel orthogonal video (after pulse compression processing) echo signals of a shore-based sea surveillance radar (fully coherent pulse compression system) collected by this system.

The experiment shows that the system fully meets the proposed index requirements, can achieve large-capacity high-speed continuous acquisition, and is stable and reliable. The acquired data can meet the requirements of signal processing and target recognition.

5 Conclusion
The overall scheme of the radar/video data acquisition and playback system is studied, which consists of a signal conditioning module, a core acquisition module, a buffer module, a transmission module and an application display module. The data exchange between the FPGA and the host computer is realized through the USB 2.0 interface, and the computer real-time display interface of the system is designed using the Visual C++ language using virtual technology. The design uses the hardware description language to program the FPGA. While completing the acquisition and recording of the input signal, it also realizes the anti-jitter, zero-crossing detection, equal-precision frequency measurement of the input signal, and the measurement of the maximum, peak-to-peak and average values ​​of the voltage, so that the system can accurately measure the signal parameters. The system is encapsulated in a small shielded box, which is very easy to carry and can be conveniently used for data acquisition of field radars.