Design of USB interface based on DSP platform

introduction

The USB interface (Universal Serial Bus) is a universal high-speed serial interface. Its main feature is its high-speed transmission characteristics. The theoretical speed limit of USB1.1 can reach 12Mb/s, and USB2.0 can reach 480Mb/s. In this way, it can well solve the problem of transferring large amounts of data between embedded systems and PCs; at the same time, it supports hot plugging and supports up to 127 peripherals at the same time, which is very suitable for embedded system applications.

This design is based on an existing DSP image acquisition embedded system, and it is equipped with a USB1.1 interface to achieve the purpose of the DSP image acquisition system to quickly transmit image data back to the PC. The main design requirements are:

① Add a low-cost, high-speed USB interface based on the interface provided by the original platform;

②Through the USB interface, the PC can operate and control the DSP image acquisition system;

③ Realize high-speed two-way transmission of image data between DSP camera system and PC.

Based on the above points, it can be seen that the most important features of this solution are low cost and high transmission speed.

1 Hardware Solution Selection and Design

1.1 Solution Selection

For the USB interface design based on the DSP platform, after comprehensive consideration of several options, it was decided to use a USB interface chip PDIUSBD12 without an MCU core (the cost is very low, the price of a PDIUSBD12 chip is only 20 yuan), plus simple peripheral circuits and timing adjustment circuits.

This chip only completes the data link-level exchange at the bottom layer of USB and provides a parallel interface to the local microcontroller, but it does not complete the work of the protocol layer. The work of the protocol layer requires programming the microcontroller to control the USB interface chip to implement the USB protocol. Therefore, the development difficulty is relatively greater, and there is more programming work to be done. However, the cost of this solution is very low, and because the DSP is directly used as the microcontroller, there is no bottleneck limitation of the original single-chip microcomputer, so a very high data transmission rate can be achieved. The principle block diagram of the system is shown in Figure 1.

Since the parallel interface timing of PDIUSBD12 is slow, it can only reach 2MB/s. This speed is relatively low compared to DSP, and some places cannot be adjusted simply by adding delays in the program, so a timing adjustment circuit is needed to complete the coordination between them.

1.2 PDIUSBD12 chip

The PDIUSBD12 chip is a USB1.1 interface chip launched by Philips. It can operate at 5V or 3.3V operating voltage; it has an 8-bit data bus and fully autonomous DMA transfer operations. It also has a controllable software connection (SoftConnect) function, which can ensure that the USB bus is connected after the microcontroller has completed initialization reliably. In addition, it has an LED drive pin that can be connected to an external LED to monitor the USB enumeration process and data transmission process. When the USB interface is enumerated and successfully configured, the LED will remain on; during the enumeration process and USB data communication process, the LED only flashes rhythmically.

PDIUSBD12 only occupies two address resources of the microcontroller. In other words, it has only one address line. One address is used to write commands to the chip, and the other address is used to write data to the chip or read data from the chip.

PDIUSBD12 has three groups of endpoints: endpoint 0 completes control transfer; endpoint 1 can be configured as interrupt transfer; endpoint 2 is the main data transfer endpoint. It has a 64B buffer, and if its double buffer mechanism is added, it has a 128B buffer; it can be configured in bulk transfer mode or synchronous transfer mode.

In general, PDIUSBD12 is a USB interface chip with excellent performance and relatively low price.

1.3 Timing Chip

In order to reduce costs and simplify the circuit, this solution does not use DMA transmission, but uses TI's TMS320C2XX as the microcontroller (using a 20MHz crystal oscillator). Its parallel port speed is very high, far higher than the maximum limit of 2MB/s required by PDIUSBD12. This is the most critical part of hardware design.

After detailed timing analysis, it is found that most problems can be solved by adding delay in DSP firmware design or setting WSGR register of DSP. However, there is one problem that must be solved in hardware. Figure 2 is the write timing of DSP (TMS320C2XX).

In Figure 2, parameter th(WD) refers to the time that the written data will remain valid after the WE signal becomes high (invalid). This value is 3ns at the minimum and 14ns at the maximum, so the written data will remain valid for about 3 to 14ns after the WE signal is invalid (the actual delay is between these two values).

Figure 3 shows the write timing required by PDIUSBD12. In the figure, parameter tWDH is another parameter corresponding to DSP (TMS320C2XX) parameter th(WD). This parameter reflects the time that PDIUSBD12 requires the microcontroller to keep the written data valid after the WR signal is invalid when writing data to it. The minimum value of this parameter is 10ns. In other words, PDIUSBD12 requires the written data to remain valid for at least 10ns (after WR is invalid).

It can be seen that the write timing of DSP (TMS320C2XX) cannot reliably guarantee to meet the requirements of PDIUSBD12, and this problem cannot be solved by adding delay in software, but must be handled by hardware. After analysis and comparison, it was finally decided to adopt a very simple but later proved to be very effective method to adjust the timing between them. That is to add a bidirectional buffer-74LS245 between the bus of DSP (TMS320C2XX) and PDIUSBD12. This chip can introduce a delay between their timing. Although this delay is not reliable, since DSP (TMS320C2XX) itself will continue to keep the data valid for a period of time after WR is invalid (as mentioned above), it only needs to extend the delay appropriately. The typical delay caused by 74LS245 is 15ns, and the minimum is 8ns. In this way, plus the delay of the original DSP write timing, the write timing required by PDIUSBD12 can be met.

In addition, the influence of adding 74LS245 on the timing of other interfaces can be eliminated by setting the WSGR register of DSP (TMS320C2XX), so this solution is feasible. (In fact, the circuit manufactured later also proved that this solution is completely feasible)

The coordination of other timings is also completely feasible after careful calculation and verification. In terms of hardware, the solution also uses a GAL (16V8) to implement the chip selection of the PDIUSBD12 chip, as well as its software and manual reset. The overall hardware block diagram is shown in Figure 4.

2 Software Design

2.1 Firmware Design

Since the USB interface chip without MCU core is used, the implementation of USB1.1 protocol specification must be completed by DSP (TMS320C2XX) controlling PDIUSBD12 chip. The main design task of the firmware is to write programs on the DSP (TMS320C2XX) platform to complete the standard requests required by USB1.1 specification and the requests defined by users according to product needs.

In order not to affect the execution efficiency of the program, this solution uses the interrupt method to complete the firmware writing; at the same time, in order to ensure the modularity and good portability of the program, a hierarchical structure is used in the design to write the firmware, as shown in Figure 5.

The bottom layer is the hardware interface layer, which completes the connection between PDIUSBD12 and DSP (TMS320C2XX) on the hardware. It mainly involves DSP (TMS320C2XX) writing data or commands to PDIUSBD12 and reading data from it.

The middle layer mainly has two modules, which are used to complete the command interface and interrupt handling subroutine of PDIUSBD12. The command interface refers to the control of DSP to it according to the command format of PDIUSBD12. Its basic command format is: DSP first writes a command to the command address, and then writes or reads a series of data from its data address. The interrupt handling subroutine determines the source of the interrupt and then jumps to the corresponding processing subroutine. These subroutines do not do too much processing, but only read the command data and set the flag, or send some data out.

The top layer is the main loop program, as well as the processing procedures for USB1.1 standard protocol requests (these requests are mainly defined in Chapter 9 of the USB1.1 protocol specification) and user-defined requests. The main work of the main loop is to check the flag bit. If the flag bit is set, the processing subroutine is called to determine whether it is a standard request or a user-defined request, and then the corresponding processing procedure is called to process it and complete the request.

The advantage of this layering is that the main loop program can perform other work when not checking the flag, thus improving the operating efficiency of the firmware.

During the programming process, since some strict interface timing coordination issues are involved, the entire firmware is written in DSP (TMS320C2XX) assembly language; the CC2000 programming development tool is used.

2.2 PC software design

The driver of the PC is provided by Philips. Then, VC++6.0 is used to write the PC application by calling the API function. In this way, the PC can realize the camera control of the DSP (TMS320C2XX) camera system and the transmission of images.

The main API functions used are DeviceIOControl(), ReadFile(), and WriteFile(). DeviceIOControl() is used by the PC (host) to send requests to the DSP image acquisition system; ReadFile() and WriteFile() are used to read data from the image acquisition system and write data to the image acquisition system respectively.

The issue that must be paid attention to during the design process is: Since the USB interface is a master-slave interface, all its transmission processes must be started after the host sends a request to the peripheral device. Therefore, before using ReadFile() and WriteFile() to read and write data, you must first send a request to the image acquisition system through DeviceIOControl().

3 Results and analysis

After the design was completed, in the final test, the communication rate between the PC and the DSP system reached a maximum of 580KB/s (4.6Mb/s) through the USB1.1 interface. This rate refers to the effective data transmission rate, excluding the header information part of the data transmission communication, so this rate is quite satisfactory. Now, it takes less than 1 second to transmit a black and white picture with a size of 352×288 pixels (size is 99KB). If dynamic shooting and display are realized, then the entire system can shoot and display 3 to 4 uncompressed black and white pictures with a size of 352×288 pixels per second.

The test results show that the system runs reliably (the program has been burned into the on-chip Flash), and all performance indicators have reached the initial design requirements, and can well realize high-speed bidirectional transmission of image data between the PC and DSP. In addition, this USB interface solution only uses one PDIUSBD12 interface chip and one 74LS245, and the device cost is only about 20 yuan, which is relatively low. At the same time, because DSP is used as the controller, its communication rate can be very high; therefore, it can be said that this solution has achieved the low-cost, high-speed USB1.1 interface design requirements.