Abstract: A second-order dual-channel time-interleaved ΣΔ modulator system structure is designed and simulated using SIMULINK. The theoretical basis and method of the design of this structure are explained, and the traditional ΣΔ modulator is compared with it in terms of bandwidth and SNDR.
Keywords: two-channel; time interleaving; SNDR
ΣΔ modulator uses oversampling and noise shaping technology and has been widely used in analog-to-digital converters (ADCs). It avoids the limitation of component mismatch on ADC accuracy and can achieve high-precision ADC. ΣΔADC trades speed for accuracy. Due to the characteristics of oversampling, ΣΔADC can only be used in low-speed, high-precision digital signal processing applications such as audio processing. Speed becomes a bottleneck for its wider application.
Multi-channel time interleaving technology uses multiple systems working in parallel at low speed to achieve high-speed systems. It has been widely used in Nyquist ADC (such as pipelined ADC, Flash ADC) [1]. For an M-channel Nyquist ADC, M channels work under M clocks with different phases. If the operating frequency of each channel is Fs, the conversion speed of the entire ADC is MFs, which is M times faster, achieving a high-speed ADC. Multi-channel time interleaving is a technology based on sampling rate conversion theory, which is achieved through downsampling and upsampling. The ΣΔ modulator uses oversampling and noise shaping technology. During the sampling rate conversion process, aliasing and mirroring of the signal spectrum will occur. Therefore, the idea of multi-channel time interleaving cannot be directly applied to the ΣΔ modulator [2]. Starting from the
basic theory of sampling rate conversion and filter bank, this paper derives the conditions for no aliasing of two-channel filter banks through the identity transformation of multi-sampling rate systems [3, 4]. The traditional ΣΔ modulator structure is equivalently transformed to obtain the system structure of the two-channel time-interleaved ΣΔ modulator. Theoretically, the operating speed is increased to twice that of a single channel [5]. SIMULINK is used to model and simulate the second-order two-channel time-interleaved ΣΔ modulator.
1 Two-channel filter bank
[page]
Then its equivalent two-channel time-interleaved structure is shown in Figure 2(b). At this time, the system is still a non-causal system that cannot be physically realized (the system loop contains the non-causal term z). Combining the non-causal term z with the z-1 term of each channel, we get the equivalent structure shown in Figure 2(c). If the operating frequency of the system in Figure 2(a) is Fs, the operating frequency of the quantizer in the equivalent structure of Figure 2(c) is also Fs. The structure shown in Figure 2(c) can be further equivalent to the structure of Figure 2(d). At this time, except for the sampling circuit and the output circuit operating at a frequency of Fs, the operating frequency of all other circuits is Fs/2.
[page]
3 Two-channel time-interleaved modulator structure and its simulation
Assume that the operating frequency of the traditional modulator in Figure 3(a) is Fs=64MHz, and the operating frequency of each channel of the two-channel time-interleaved modulator in Figure 3(b) is also Fs=64MHz. SIMULINK is used to model and simulate the two modulator structures respectively. The input signal is a sinusoidal signal with a frequency of Fin=1.9921875e+005 and an amplitude of -4dB full-scale amplitude. The embedded ADC and DAC are 1bit. The power spectrum of the output signals of the two modulators is shown in Figure 4. It can be seen from Figure 4 that the two-channel time-interleaved modulator structure has a better noise shaping effect. If the operating frequency of each channel of the traditional modulator structure and the two-channel time-interleaved modulator structure is the same, and the signal bandwidth is the same, then the OSR of the two-channel time-interleaved modulator structure is twice that of the OSR of the traditional modulator structure, which is equivalent to an increase of 1 times in OSR. Theoretically, assuming that the quantization noise of the modulator is white noise, according to the ΣΔ linear model, it can be obtained that for every 1 times increase in the OSR of the modulator, its SNDR increases by (6L+3)dB, where L is the order of the modulator [7]. Figure 5(a) shows the relationship between the SNDR of the two modulators and the input signal amplitude when the OSR=64 of the traditional modulator and the OSR=128 of the two-channel time-interleaved modulator, that is, when the signal bandwidths of the two modulators are the same. Figure 5(a) shows that the SNDR of the two-channel time-interleaved modulator is about 15dB higher than that of the traditional modulator, which is consistent with the theoretical value. Figure 5(b) shows the relationship between the SNDR of the two modulators and the input signal amplitude when the OSR=64 of the traditional modulator and the OSR=64 of the two-channel time-interleaved modulator, that is, when the signal bandwidth of the two-channel time-interleaved modulator is twice that of the traditional modulator. It can be seen from Figure 5(b) that when the signal bandwidth of the two-channel time-interleaved modulator is twice that of the traditional modulator, its SNDR remains almost unchanged. This shows that the speed of the two-channel time-interleaved modulator can be increased by 1 times while its accuracy remains unchanged.
In this paper, a second-order two-channel time-interleaved ΣΔ modulator is designed under the condition of no aliasing of the two-channel filter group, and it is simulated by SIMULINK. The simulation results show that: without increasing the operating frequency of each channel, the signal bandwidth of the modulator is doubled, and the modulator accuracy remains almost unchanged, which is equivalent to doubling the speed of the modulator; if the signal bandwidth is kept equal, its SNDR can be improved by about 15dB. Based on this paper, the structure of multi-channel time-interleaved ΣΔ modulator can be further studied and designed. [page]
References
[1] GUPTASK, INERFIELDMA, WANG Jingbo. A1-GS/s 11-bit ADC with 55-dBS SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture [J]. IEEE J. Solid-State Circuits, 2006, 41(12): 2650-2657.
[2] Khoini-Poorfard R, JOHN SDA. Time-interleaved oversampling converters [J]. Electronics Letters, 1993, 29(19): 1673-1674.
[3] Tao Ran, Zhang Huiyun, Wang Yue. Theory and Application of Multi-sampling Rate Digital Signal Processing [M]. Beijing: Tsinghua University Press, 2007.
[4] VAIDYANATHAN PP. Multirate digital filters filter banks polyphase networks and applications: A Tutorial [J]. IEEE Trans. Signal Processing, 1990, 78 (1): 56-93.
[5] BURRU SC. Block realization of digital filters [J]. IEEE Transactions on Audio and Electroacoustics,
[6] SCHREIERR, TEMES G C. Understanding delta-sigma data converters [M]. New York: IEEE Press, 2005.
[7] YI Ting. Design of high performance Σ△ analog-to-digital converters [D], PhD dissertation of Fudan University, 2002, 3: 17-19.
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