A brief discussion on the method of using the parts average test method to detect the quality of automotive semiconductor components

The industry's call for zero-defect semiconductor components is growing, and semiconductor manufacturers are beginning to invest more to meet the challenge and meet the needs of automotive users. As the number of electronic components in automobiles continues to increase, the quality of semiconductor components in modern automobiles must be strictly controlled to reduce the defect rate per million parts (DPM), minimize the use of electronic components related to field returns and warranty issues, and reduce liability issues caused by electronic component failure.

The American Automotive Electronics Council AEC-Q001 specification recommends a general method that uses the Part Average Testing (PAT) method to remove abnormal parts from the total parts, thereby improving the quality and reliability of components at the supplier stage. For a specific wafer, batch number, or group of parts to be tested, the PAT method can indicate the test results where the total average value falls outside 6σ. Any test result that exceeds the 6σ limit value of a specific component is considered unqualified and is removed from the total number of parts. Parts that do not reach the PAT limit value cannot be shipped to customers, which improves the quality and reliability of components.

The demand for these specifications has led to more intense competition among suppliers. There is great pressure to improve reliability and reduce defect rates, especially for many of the critical safety functions now controlled by semiconductors, such as x-trail, traction control, powertrain and active stability control systems. Suppliers must improve the quality of parts that have already begun shipping while minimizing the impact of these specifications on their yields. As manufacturing costs continue to fall and test costs remain at a relatively unchanged level, the proportion of test costs in manufacturing costs continues to increase, and the profit margins of components continue to shrink. Since the vast majority of yields cannot meet requirements, suppliers must thoroughly evaluate their test procedures to find alternative test methods and repeatedly test the alternative methods until the best method is found.

Without the aid of cutting-edge analysis and simulation tools, suppliers will apply these specifications without fully understanding the impact they will have on the supply chain. Even worse, if they are applied blindly and important tests are omitted, the result is that even if the components are tested to specifications such as PAT and start shipping at the same DPM rate, the guarantee is meaningless and reliability will be reduced.

Some suppliers seem to think that PAT testing during wafer probing is sufficient, but research shows that there are many problems with this approach. PAT during wafer probing is the first quality checkpoint, but the increased variability caused by countless variables in the remaining downstream manufacturing processes will lead to more PAT outliers during package test. If suppliers want to release high-quality parts, they must perform PAT testing at both the wafer probing and final test stages, and their customers should also promote the application of this approach.

Real-time PAT and statistical post-processing The PAT process uses an approach that analyzes the latest data over several batches and establishes static PAT limits for each test of interest. These limits are calculated as an average of +/-6σ and are typically incorporated into the test program as upper specification limits (USL) and lower specification limits (LSL). Static PAT limits must be reviewed and updated at least every six months.

The preferred approach is to calculate dynamic PAT limits for each lot or wafer. Dynamic PAT limits are typically tighter than static PAT limits and weed out any outliers that are not within the normal distribution. The most important difference is that dynamic PAT limits are calculated on a wafer or lot basis, so the limits will change continuously based on the material properties used in the wafer or lot. Dynamic PAT limits are calculated as mean +/- (n*σ) or median +/- (N*toughnessσ) and cannot be less than the LSL or greater than the USL specified in the test procedure.

The calculated PAT limits are bounded as the lower PAT limit (LPL) and upper PAT limit (UPL) shown in Figure 1. Any value that exceeds the dynamic PAT limit and is between the LSL and USL limits is considered an outlier. These outliers are usually named as failures and are placed into a specific outlier software and hardware box. Tracking the calculated PAT limits for a specific wafer or lot and the amount of outliers detected for each test is important for later traceability. There are two main methods for implementing PAT: real-time PAT and statistical post-processing (SPP). Suppliers must understand whether to use two different methods in detection and final test, or whether it makes more sense to use only one approach.

Real-time PAT makes sorting decisions as the part is tested, based on the calculation of dynamic PAT limits, without affecting the test time. This requires a dynamic real-time engine that can handle complex data streams for monitoring and sampling. Similarly, this process also requires a strong statistical engine that can capture test data and perform the necessary calculations to generate new limits, feed new limits and sorting information into the test program; at the same time, monitor the entire process to ensure stability and controllability. Suppliers need to perform real-time processing for detection and final testing and handle baseline outliers.

Statistical post-processing methods produce the same final test results. After a batch is completed, the component tests are statistically processed and sorting decisions are made. However, because the sorting decision is made after the batch is processed, post-processing can only be used for wafer probing because the test and sorting results are related to specific components for re-sorting. In packaged test, once the components are packaged, there is no way to track or sequence them, so there is no way to link test and sorting results to specific components. SPP also requires data logging of complete test results in order to make decisions, which increases the IT infrastructure requirements (a lot of time) and significantly slows down test time. Because the results are post-processed, SPP processes baseline outliers in a batch as part of the overall component.

Both approaches require powerful computations to process test and sort results, as do regional PAT and other failure modes. An example of regional PAT is a good die surrounded by multiple faulty die on a wafer. Studies have shown that this good component is likely to fail prematurely, and most suppliers must find this good component in their efforts to reduce DPM in automotive components.

Implementation of real-time testing Assume that we are manufacturing power management components for automobiles at this moment. We load historical test data into analysis tools and conduct in-depth analysis of component parameter data to find out which test is a better candidate for PAT. There are good and bad tests. Some tests are more suitable for PAT, and some tests are more important for functional testing of components. If all tests of components are selected, the yield will be unacceptable.

The problem with some tests is that the data is not stable enough to be measured according to PAT standards. This variability may be inherent in the component itself, caused by the test process (such as an instrument in the automatic measurement equipment cannot produce accurate measurements), or introduced by the packaging process, which just cannot be statistically controlled and cannot be measured.

Baselines are used to establish dynamic PAT limits for a specific wafer or lot. For example, on a wafer containing 1,000 die, a baseline of 100 typical die is the most appropriate statistical sampling for that wafer.

Once a baseline is achieved, several important tasks need to be performed before dynamic PAT limits are applied in a live environment. A normality check is performed on each selected test. If the data is normally distributed, the standard deviation is calculated using the 'standard' method; however, if the data is not normally distributed, the standard deviation is calculated using the 'robust' method.

Dynamic PAT limits for each selected test must be calculated and stored in memory for subsequent testing. The initial LSL and USL remain unchanged and are used to detect test failures based on the original test program. Baseline outliers are calculated for the selected tests. In probing, XY coordinates are saved for processing after wafer fabrication. In package testing, baseline components are sorted into baseline bins. If outliers in the baseline are detected, then these components are identified for retesting.

Once the baseline is reached, dynamic PAT limit checks are performed for each selected test and each component is binned in real time. Those components that do not meet the PAT limits fall into a unique 'outlier' software or hardware bin that identifies them as PAT outlier components for post-testing.