Design of Universal Video Acquisition System Based on XC3S200

There are two mainstream implementation schemes for video acquisition: one is based on ASIC, which generally uses dedicated video processing chips from companies such as STMicroelectronics and AMD; the other is based on DSP, which mainly uses DSP signal processors from companies such as Intel and ADI. As auxiliary processors, they can collect and compress video signals under the control of the main CPU. With the development of FPGA, video acquisition through SOPC technology has become an easy-to-develop and flexible solution. This is mainly due to the development of IP multiplexing technology. Building complex embedded systems on FPGA can utilize existing functional modules and their drivers. This solution has greater integration and flexibility, and will inevitably become a major trend in the development of electronic design.

This paper introduces the design of a general video acquisition system using Xilinx's Spartan-3 FPGA. The system can collect video signals in real time and compress and encode them in MPEG-4 format by connecting an external analog PAL/NTAL camera. The code stream can be transmitted to a PC via a USB interface or transmitted over the network via an Ethernet interface. This system uses the XC3S200 chip of the Spartan-3 FPGA series, which has 4320 logic cells (LCs), 216Kbit BlockRAM, 4 digital delay-locked loops (DDLs), 173 user I/Os, and has high logic density, many I/Os, and low cost. This design mainly involves circuit board-level hardware design, FPGA chip-level hardware system design, and system software design.

1 Board-level hardware design

With the support of power supply and configuration circuit, FPGA can form a minimized system of embedded system and realize all functions in the chip. On this minimized system, the functional module circuits such as external storage module, video acquisition module, USB interface module, Ethernet interface module can be expanded according to the application requirements of this design, thus forming a circuit board level hardware platform. The structure of the board level hardware platform is shown in Figure 1.

1.1 Minimize the system

The FPGA is a device based on the SRAM storage structure. Each time the power is turned on, the configuration data can be loaded from the external configuration memory into the internal SRAM to build a logical structure and realize the logical function. The configuration debugging module mainly includes the configuration memory, the configuration mode jumper switch and the JTAG debugging port. The JTAG debugging port is the communication interface between the PC and the FPGA in the system development stage. It can be used to download the FPGA configuration data from the PC and serve as an online interface in the program debugging stage. This design uses the Xilinx Platform. Flash series configuration memory XCF02S and uses a 14-pin JTAG interface. The mode jumper switch can determine whether the FPGA is configured by JTAG or by the configuration memory. The system clock module can provide a 50 MHz high-frequency clock signal to the XC3S200. It uses a high-stability quartz crystal oscillator discrete component. The power management module uses a DC/DC converter to provide the various voltages and currents required for each component of the system. The above parts are connected to the FPGA chip to form a minimized system for the embedded system.

1.2 External storage expansion

Since the XC3S200 has limited internal storage capacity and loses memory when power is off, a large external storage must be configured. This design expands 4MByte flash and 32MByte SDRAM (including one AM29LV320DT90EC Flash from AMD and two HY57V281620HCT-PI SDRAMs from HYNIX). Flash is used in the system to store program code, constant tables, and some user data that needs to be saved after the system loses power. While SDRAM loses data when power is off, its access speed is much higher than Flash and it is readable and writable, so it is used in the system as program running space, temporary data, and stack area.

1.3 Video Capture Module

TVP5150 is an ultra-low power, high-performance mixed-signal video decoding chip launched by the company. It can automatically identify analog signals in NTSC/PAL/SECAM format, convert them into digital signals in the YCbCr4:2:2 format, and then output them in the ITU-RBT.656 format with 8-bit embedded synchronization signals. TVP5150 has the characteristics of low price, small size, and easy operation. FPGA operates the TVP5150 chip through the I2C bus, and the data transmission connection adopts the simplest ITU-RBT.656 method.

1.4 USB interface module

The USB interface module uses the high-performance USB interface chip PDIUSBD12 from PHILIPS. This chip fully complies with the USB1.1 specification, supports DMA transmission, and can communicate with FPGA through a high-speed 8-bit parallel interface. Its maximum parallel interface rate can reach 2 MB/s.

1.5 Ethernet interface module

This module uses the highly integrated Ethernet controller RTL8019AS produced by Realtek. RTL8019AS supports IEEE802.3 standard and 8-bit or 16-bit data bus. Its built-in 16KB SRAM can be used for transceiver buffering. In full-duplex mode, its transceiver can reach 10Mbps at the same time. RTL8019AS can support 10Base5, 10Base2, 10BaseT, and can automatically detect the connected medium. This design uses the RTL8019AS jumper interface mode and connects to the FPGA through a 16-bit data bus.

2 Chip-Level Hardware System Design

The basis for building embedded systems on Spartan-3 is the MicroBlaze IP core. This is a 32-bit microprocessor implemented in the FPGA using a hardware description language, using the RISC instruction set and Harvard architecture. It can be customized according to different peripheral and memory configurations, and the processor system architecture can be adjusted according to the application. This configuration on the Spartan-3 series chip occupies about 500 slices. The IP core has 32 32-bit general registers and 2 special registers. Its 32-bit wide instruction system can support 3 operands and two addressing modes, and its independent 32-bit instruction and data buses are fully compatible with IBM's OPB bus. Through the LMB bus in the module, its 32-bit instructions and data can be directly connected to the block memory on the chip. In addition, the IP core also has high-speed instruction and data caches (Cache), a three-stage pipeline structure, a 32-bit address bus, hardware debugging logic, 8-input and 8-output fast link (FSL) interfaces, etc. The internal functional structure of the MicroBlaze soft processor is shown in Figure 2.

When designing an embedded system on an FPGA, you can develop on-chip peripheral IP cores on the lowest level of hardware resources, or use the developed IP cores to build the hardware part of the embedded system, and then develop the device driver, application interface (API) and application layer (algorithm) of the IP core. By connecting the local memory bus (LMB) and the on-chip peripheral bus (OPB) to the on-chip peripheral IP core through the standard bus interface, the MicroBlaze processor can be connected to various peripheral IP cores and on-chip BlockRAM. The IP cores provided by the development tool all have corresponding device drivers and application interfaces, and users only need to use the corresponding function library to write their own application software and algorithm programs. For IP cores developed by users themselves, they need to write the corresponding driver and interface functions themselves. The basic embedded system built using the MicroBlaze processor is shown in Figure 3.

To implement an embedded system on an FPGA, the main thing is to build an on-chip MicroBlaze processor and add on-chip peripherals to the processor to implement the hardware module functions. At the same time, the connection between the on-chip peripherals and the external pins of the chip should be added. While developing the on-chip peripherals, the underlying driver of the peripheral functions should be developed, and then the system application should be implemented on the MicroBlaze processor. This is a process of collaborative development of software and hardware. The EDK (Embedded Development Kit) provided by Xilinx can be used for system development with the MicroBlaze processor as the core. The EDK provides an integrated development environment XPS (Xilinx Platform. Studio), which integrates tools such as hardware platform generator, software platform generator, simulation model generator, software compiler and software debugger. In this environment, calling various tools can complete the entire process of collaborative development of software and hardware. EDK provides a variety of functional IP cores related to the MicroBlaze processor, including OPB 10/100M Ethernet controller, PLB/OPB SDRAM controller, UART interrupt controller, timer and other peripheral device interface resources. The Base System Builder Wizard in EDK can be used to configure the MicroBlaze processor, while the ImportPeripheral Wizard can be used to call existing IP cores to generate on-chip devices and connect them to the processor bus.

The main functional modules in this system include video interface module, ring buffer, two-level FIFO buffer for code stream, MPEG-4 encoder, Flash controller, SDRAM controller, 10/100M Ethernet control module, USB control module, etc. The video interface module is the interface between MicroBlaze processor and TVP5150. The control driver of MicroBlaze processor for TVP5150 can be transplanted from TVP5150 driver template, which can be used to configure the acquisition mode of TVP5150 and store the acquired video signal in 4:2:0YUV format in the ring buffer. The ring buffer is part of the SRAM storage space connected to the MicroBlaze processor bus in the chip, and the head and tail pointers of the data queue are maintained by the MicroBlaze processor program. The FIFO template provided by the development tool can be used to set its depth, bit width, read and write clock, full flag and other parameters, and connect two FIFOs to form a two-level FIFO, and then connect its entrance to the output of the MPEG-4 encoder. The first level of FIFO is connected to the MicroBlaze processor bus to support DMA reading. The MPEG-4 encoder is an MPEG-4 Simple Profile encoder IP core authorized by Xilinx. It accepts uncompressed 4:2:0YUV format video signals in the ring buffer and generates MPEG-4 Simple Profile format compressed bitstreams. The MPEG-4 encoder is connected to the MicroBlaze processor bus and two-level FIFO inputs, and its driver can be provided for EDK. The implementation software of the Flash controller, SDRAM controller, and 10/100M Ethernet controller has been provided in EDK, and its connection with the processor bus is also automatically set in the wizard tool, and its driver is included in it. Since a highly integrated USB controller is used outside the chip, and the USB control module inside the chip is only a direct connection between the MicroBlaze processor bus and the pins, its driver is just a reference to the general driver of PDIUSBD12 transplanted on the EDK software platform.