How to generate three-phase inverter pulses for 120° operation in SaberRD?

A three-phase inverter converts a DC input into a three-phase AC output. A basic three-phase inverter consists of three single-phase inverter switches, each connected to three load terminals. The switches are programmed to open and close at fixed intervals of 60° to obtain a three-phase voltage. Three-phase inverters are often used in variable frequency drive applications and high power applications such as high voltage DC transmission.

The three-phase inverter may have multiple conduction modes, such as a 180° conduction mode and a 120° conduction mode.

The following figure shows the circuit of the three-phase inverter and the gate pulse switching cycle timing in two working modes. Switches AH and AL, BH and BL, CH and CL complement each other.

• 180° conduction mode

In this conduction mode, each device is in 180° conduction state and they are turned on at intervals of 60°. Terminals Va, Vb and Vc are bridged output terminals connected to the three-phase delta or star connection of the load.

• 120° conduction mode

In this conduction mode, each device is in a 120-degree conduction state. At any given moment, only two devices are conducting because each device only conducts 120 degrees. From the above figure, we can see that the switch is triggered ON at 60° intervals and remains in the ON state for 120°.

When MOSFET switch AH conducts from wt = 0° to 120°, MOSFET switch AL starts conducting from wt = 180° to 300°, and the cycle repeats. The empty space between gates shown in gray is the time when no switch in the same branch is conducting.

The 120° operating mode has a 60 degree interval between turning off and turning on of devices in the same branch of the inverter, compared to 180° with the 120° regulation mode.

The download link of "Design Files for Implementing 120° Operation Mode Gate Pulse of Three-Phase Inverter in SaberRD" is provided at the end of the article. The working principle of the circuit is analyzed by simulation. For simplicity, the snubber circuit and commutation circuit are omitted.

1. Download the sample files.

2. Invoke SaberRD and open the design: test_120_inverter_degree_operation.ai_dsn.

In the above design, the template SVPWM controller represents a three-phase PWM generator with digitally controlled outputs. The model uses SPWM (Sinusoidal PWM) modulation technique to generate PWM drive signals for any Voltage Source Inverter (VSI) application in 180° operation mode.

The selected operating frequency is frq = 60Hz. In this example, ma, mf, dc_offset are selected to generate a single pulse instead of a modulated signal. More information about the above parameters can be found in the help of the template and part files.

The input to this controller model is generated using the ppwl model from the SaberRD library to generate the required 120° mode operating gate pulses for ah, bh, and ch.

The PWM frequency selected in the SVPWM model is 60 Hz.

One period = tp = 1/60 and one sixth of a period is 1/6*1/60 = 1/360. The input to the PPWL model is now calculated by multiplying the period by 1/360 to generate the required waveforms AH, BH and CH as shown below.

If you need to generate pulses with different frequency, you can assign it in the SVPWM model parameter frq and replace the value 1/360 in all rows with 1/6*frq in the PPWL model.

NOTE: There are different ways to generate these gate pulses for 120° mode operation using various models of SaberRD, only one of these methods is discussed here.

Create a hierarchical model spwm_extension_120_degree to additionally generate low-side gate pulses al_g4, bl_g6, and cl_g2. It can convert all gate signals from digital to analog by using the interface blocks provided in SaberRD. The properties assigned to each block are shown in the following figure.

1. Select the Simulate tab and then Experiment and run transient_analysis. This experiment performs a transient analysis on the design, performs necessary operations on the waveform, and plots the results.

The SVPWM model is the high-side gates g1_pwm_ah, g3_pwm_bh and g5_pwm_ch, and the generated digital gate pulses are shown in the figure above.

Therefore, the simulated gate pulses generated by the extended model are shown as vgs_ah, vgs_al, vgs_bh, vgs_bl, vgs_ch, and vgs_cl.

The line voltages va, vb, vc vary between +Vs/2 and -Vs/2, where Vs (24V) is the supply voltage of the inverter. By subtracting the line-to-neutral voltages va and vb in the experiment, we get the line-to-line voltage va-vb as shown in the figure above. It varies between V and -V.

Similarly, the line voltages VB-VC and VC-VA are obtained by subtracting the corresponding waveforms in the experiment. The line voltage has six levels of AC voltage.

The line voltage seen here has a voltage step of (Vs/2 -Vd) = 11.69V, (Vs-2*Vd) = 23.26V, and 0V, -11.69V and -23.26V are based on different switching cycles in one complete cycle.

Each PWLD diode used here produces a voltage drop Vd of about 0.31V.