Low-power design of autonomous driving chips

Judging from the relevant policies that have been issued one after another, the autonomous driving industry is currently a key area of ​​national support. In recent years, my country's autonomous driving industry has also flourished with the support of many parties. With the increasing maturity of software and hardware conditions, new cars equipped with L2-level autonomous driving functions are gradually becoming the pre-installed standard for smart cars. At present, the autonomous driving level of mass-produced passenger cars in my country is also transitioning from L2 to L3+, and even many technology companies have begun to develop L4-level autonomous driving chips and solutions. As the market demand for the level of autonomous driving in cars increases, the computing power requirements of autonomous driving chips installed in cars are also increasing, and chips with higher computing power will also bring higher power consumption. For consumers and car manufacturers, power consumption has always been the focus of their attention. How to achieve low power consumption and high performance is a problem that chip designers and their upstream companies need to solve together.

1 Advantages of reducing power consumption

Why do we need power management? Let’s talk about it briefly.

1) Excessive power consumption will shorten the usage time. We who often use mobile phones and other electronic devices also know that frequent charging will greatly reduce our user experience.

2) Excessive power consumption will cause higher temperatures. Higher temperatures will cause electron migration or other thermal failure mechanisms, thereby reducing the stability of the chip.

3) For automobiles, if the power consumption of the autonomous driving chip exceeds a certain limit, the car manufacturer will need to use water cooling measures to cool it down instead of an air cooling system, which will also increase the manufacturing cost of the entire vehicle.

4) High power consumption will also affect battery life, making it shorter, which will increase user costs and reduce user product experience to a certain extent.

Therefore, the power consumption of the system on a chip is a very important topic. As a chip designer, making the self-driving chips installed in smart cars have lower power consumption runs through our work all the time, from the early stage of non-self-developed chip IP selection, to the mid-term chip design, to the later software and solutions. We will try to reduce the power consumption of the chip at each stage, and provide more stable and more market-competitive self-driving chips while ensuring computing power.

2 Ways to reduce power consumption[1]

2.1 Basic Concepts

First, we need to introduce two concepts: dynamic power consumption and static power consumption. The power consumption of SoC includes dynamic power consumption (Dynamic Power) and static power consumption (Static Power).

Dynamic Power

Dynamic power consumption is the power loss caused by the change of signal value. Dynamic power consumption consists of two parts: switching power consumption and internal power consumption. Switching power consumption is the power consumed by charging and discharging external capacitors (as shown in Figure 1), and internal power consumption is the power consumed by the short-circuit current flowing through the PMOS-NMOS stack when the logic state of the circuit changes (as shown in Figure 2).

Figure 1

Figure 2

Static Power

Static power consumption is the power consumed when the device is powered on but no signal value changes. In CMOS devices, static power consumption comes from leakage (see Figure 3).

Figure 3

2.2 Ways to reduce power consumption

2.2.1 Supply Voltage Reduction

The most basic way to reduce power consumption is to reduce the supply voltage. Power consumption is proportional to the square of the voltage. So if the voltage is reduced by 50%, the power consumption will be reduced by 75% (as shown in Figure 4). The continuous update and iteration of CMOS technology has made the supply voltage lower and lower to reduce power consumption. The supply voltage has been reduced from 5V in the 1980s to 0.75V or even lower now.

Figure 4

2.2.2 Clock Gating

Clock gating is a way to reduce dynamic power consumption. This is very useful for registers that need to maintain the same value for many clock cycles, because it avoids unnecessary power consumption caused by reloading the registers every clock cycle. The biggest challenge of this method is how to find the optimal location to place the clock gating to ensure that the clock is turned on and off at the right time.

Clock gating technology has been used for many years and is very mature. Synthesis tools such as Power Compiler can detect low-throughput data paths and automatically insert clock gating units at appropriate locations on the clock path. Clock gating is also relatively simple to implement. It only requires changing the netlist, without the need for additional power supplies or other power facilities.

2.2.3 Multiple-Vt Library Cells

Some CMOS technologies support standard library cells with different voltage thresholds. In this case, the cell library can provide two or more different threshold voltage cells to implement the same logic function. For example, the library can provide two inverter cells: one with a low-Vt transistor and one with a high-Vt transistor.

Low-Vt cells have higher speeds, but also have greater leakage currents. High-Vt cells have lower leakage currents, but are slower. Therefore, synthesis tools can select the appropriate type of cells based on the tradeoff between speed and power consumption. For example, low-Vt cells can be used in timing-critical paths to achieve higher speeds, while high-Vt cells can be used in paths that do not require very high timing to reduce power consumption.

2.2.4 Multi-voltage Design

Different parts of a chip have different speed requirements. For example, the CPU and RAM need to have higher speeds than the peripherals. As mentioned earlier, lower voltages not only reduce power consumption but also reduce speed. To get maximum speed and lower power consumption, a higher supply voltage can be provided to the CPU and RAM, while a lower supply voltage can be provided to the peripherals. However, providing two or more power supplies on the same chip increases design complexity and cost. For example, more pins are required to power the chip, and the power grid must allocate each voltage source to the appropriate module.

2.2.5 Power Switching

The power switch is a way to save power by turning off the power of a certain module of the chip when it is not used for a long time. For example, a mobile phone chip turns off the sound processing module when the phone is in standby mode. When the user receives a call or makes a call, this module will be awakened.

Power switching further reduces static and dynamic power consumption, but it also brings some challenges, such as its implementation requires a power controller, a power switch network, isolation cells, and retention registers.

The power controller is a logic module that decides when to power on and off. However, powering on and off will bring a certain amount of time and power consumption, so the controller must decide an appropriate time to turn on and off the power.

A block that can be powered down must receive power from a power switch network consisting of a large number of transistors with source-to-drain connections between the always-on power rail and the power pin cells. The power switches must be located around or inside the block. This network, when the power is turned on, connects the power to the logic gates, and when the power is turned off, the power supply is disconnected from the logic gates.

We often use High-Vt transistors as power switches because they can have smaller leakage current and we don't care about its switching speed. As shown in Figure 5, the PMOS header switch can be placed between VDD and the module power supply pin, or the NMOS footer switch can be placed between VSS and the module ground pin.

Figure 5

The power switch strategy described above is a coarse-grained switch strategy, because this power switch can control the power on and off of the entire module. If it is a fine-grained strategy, each library unit has its own power switch, allowing for finer-grained control of power on and off. This approach can better save power consumption, but also requires a larger area.

2.2.6 Dynamic Voltage Frequency Scaling

Based on the concept of multi-voltage mentioned above, we can expand it to dynamically adjust the voltage according to the current workload during operation. For example, a chip can use lower voltage and lower frequency when doing simple calculations, and if higher performance is required, the voltage and frequency can be increased. This method of adjusting voltage and frequency in real time is called DVFS.

The chip supply voltage can be designed to be multiple levels or a continuous range. Dynamic voltage regulation requires a multi-level power supply and a logic module that can accurately determine the optimal voltage value for a given task. Because it is necessary to analyze and consider the combination of different voltage levels and frequencies, this is a considerable challenge for design, implementation, verification and testing.

We can combine dynamic voltage regulation and power switching so that the module can adjust the voltage according to the current workload or turn off the power when it is not in use, to achieve more power savings.

3 Power consumption management module[2]

As the complexity of contemporary SoCs increases, more and more chip designers choose to separate the role of power management in the SoC and select a small processor combined with software to be responsible for the power management of the entire SoC.