Software and hardware design based on G9X body domain controller

[Abstract] The body domain controller is the control core of each functional block of the automotive electronic system divided according to its functions. Its internal network is connected to the central gateway controller through the CANFD/CAN or FlexRay communication bus, which can realize the basic functions of the body controller, including lighting control, wiper control, door lock control, window lifting, PEPS, TPMS, etc. Combined with the technical requirements of the body domain controller, this paper introduces a body domain controller based on the domestic SoC design, and verifies the various functions of the domain controller by building a test bench, which can meet the customer's requirements for high performance, safety, security and reliability.

As the automotive electronic and electrical architecture develops towards centralization, the entire vehicle is divided into the power domain, chassis domain, body domain, autonomous driving domain, and intelligent information domain according to the functions of automotive electronic components [1]. With the powerful computing power of processor chips, the distributed ECUs are unified, the hardware input and output interfaces are uniformly planned, the duplication of connectors, structural parts, wiring harnesses, and hardware resources is reduced, and the software integrates the functional strategies of multiple controllers for fusion development, saving software overhead and external information routing [2]. This can reduce the hardware cost of the entire vehicle and save the waste of resources caused by the redundancy of multiple ECU computing power.

The body domain controller generally integrates functions such as body controller, keyless entry and start, tire pressure monitoring, gateway, etc. It can also add functions such as seat adjustment, rearview mirror adjustment, air conditioning control, etc., comprehensively and uniformly manage various actuators, and reasonably and effectively allocate system resources.

In the past 1~2 years, the entire automotive electronics industry, especially automotive MCUs, has faced a severe shortage. During this period, many OEMs and Tier 1 factories have begun to seek supply guarantees. Finding a domestic alternative is urgent, and this process is also full of opportunities. This article introduces a body domain controller based on a domestic SOC design, and verifies the various functions of the domain controller by building a test bench to meet customer requirements.

1 G9X Chip Introduction

The G9 series is a product for central gateways released by CoreDrive Technology in 2020, with the first chip being the G9X. The G9 series processors are high-performance automotive-grade chips designed for the next-generation in-vehicle core gateways. They use a dual-core heterogeneous design, including a high-performance Cortex-A55 CPU core and a dual-core lock-step high-reliability Cortex-R5 core. While carrying a wealth of applications for future gateways, they can also meet the requirements of high functional safety levels and high reliability. The G9 chip architecture is shown in Figure 1.

Figure 1 G9 chip architecture

G9 supports multiple peripheral interfaces, including PCIe, USB3.0 interfaces, and has a variety of transmission interfaces such as Ethernet, CANFD and LIN. On this basis, G9 uses the second-generation packet processing engine SDPEv2 of CoreChi to achieve high-flow and low-latency data exchange between different interfaces with very low CPU occupancy.

In addition, the G9 has a built-in HSM, which includes a true random number generator and a high-performance encryption and decryption engine. It supports AES, RSA, ECC, SHA and a variety of national secret algorithms to meet the needs of various future in-vehicle security applications such as secure boot, OTA, V2X, etc.

2 Domain Controller Hardware Design

The domain controller hardware block diagram is shown in Figure 2.

Figure 2 G9X domain controller hardware block diagram

The resources of the body domain controller are as follows: ① Support 2 CAN/CANFD interfaces; ② Support 1 LIN; ③ Support 1 100Base-T1 vehicle Ethernet; ④ Support 1 1000Base-T1 vehicle Ethernet; ⑤ Support 28 signal outputs; ⑥ Support 44 signal inputs; ⑦ Integrated PEPS function (including IMMO); ⑧ External eMMC and QSPI FLASH to store OTA update data; ⑨ Support LIMP HOME mode.

2.1 Power supply and reset design

The domain controller power supply is divided into RTC power domain, SAFETY power domain and AP power domain according to the functional unit. The RTC power domain is powered on first and is responsible for controlling the overall power supply of the chip; the SAFETY power domain is the working power supply for the R5 core MCU; and the AP power domain is the working power supply for the A55 core MPU. Each power domain of the controller is implemented using discrete DC/DC. The specific power supply solution is shown in Figure 3.

Figure 3 Domain controller power solution

2.2 CAN/CANFD interface design

TJA1043 is NXP's third generation high-speed CAN transceiver. Compared with the first and second generation devices (such as TJA1041A), it has significant improvements. It can provide improved electromagnetic compatibility (EMC) and electrostatic discharge (ESD) performance, extremely low power consumption and passive performance when the power supply voltage is turned off. This solution can also choose the domestic chip SIT1044T/3 or SIT1044TK/3 of Xinlit Company. The design principle of CAN/CANFD interface is shown in Figure 4.

Figure 4 CAN/CANFD interface design schematic

2.3 LIN interface design

The LIN interface uses the NXP TJA1021 chip to achieve the interface conversion between the LIN master-slave protocol controller and the physical bus. The TJA1021 chip supports 1~20kBdb baud rate, complies with the LIN 2.1/SAE J2602 specification, and has low electromagnetic radiation and high electromagnetic interference resistance. The chip input level is compatible with 3.3V and 5V, and supports low-power sleep mode and local/remote wake-up function.

In addition, the chip has multiple protection mechanisms: support ±6kV (pins LIN, VBAT and WAKE_N) ESD characteristics in accordance with IEC61000-4-2; LIN bus and power pins support ISO 7637 standard anti-transient protection; LIN bus pins have short-circuit protection for power supply and GND; overheating protection. This solution can also choose the domestic chip SIT1021 of Xinlit Company. The design principle of the LIN interface is shown in Figure 5.

Figure 5 LIN interface design schematic

2.4 100Base-T1 In-vehicle Ethernet Interface Design

The 100Base-T1 in-vehicle Ethernet interface uses the YT8010A from Suzhou Yutai Chetong Electronic Technology Co., Ltd. The chip has a single MDI output and supports a working rate of 100Mb/s. The YT8010A is a single-pair Ethernet physical layer transceiver (PHY). It implements the Ethernet physical layer portion of the 100BASE-T1 standard defined by the IEEE 802.3bw working group. It is very suitable for a wide range of automotive applications. It is manufactured using standard digital CMOS processes and contains all the active circuits required to implement the physical layer for transmitting and receiving data on a single balanced twisted pair. Based on cutting-edge DSP technology, combined with adaptive equalizers, echo cancellers, ADCs, phase-locked loops, line drivers, encoders/decoders, and all other required support circuits, it can achieve powerful performance and exceed the interference (EMI) requirements in the automotive electromagnetic noise environment, with very low power consumption.

The YT8010A design is fully compatible with the RGMII, RMII and MII interface specifications, allowing compatibility with industry-standard Ethernet media access controllers (MACs) and switch controllers, meeting the AEC-Q100 Grade 1 temperature range, and the connection between the YT8010A chip and the main chip, including the MAC communication interface and the MDIO management interface. The MAC communication interface supports three interfaces: RGMII, RMII and MII. When connected to G9X, the RGMII interface is used for connection, and the working rate is 100Mb/s. The MDIO interface is used for G9X configuration and management of YT8010A, and the interface follows the IEEE802.3 Clause 22 definition. The YT8010A chip schematic design is shown in Figure 6.

Figure 6 100Base-T1 interface design schematic

2.5 Body Domain Controller PCB Design

The hardware of the vehicle body domain controller adopts 8-layer PCB design. The processing of high-speed signals, digital signals, analog signals, high-power signals, etc. is fully considered during the design, and a three-dimensional model is generated at the same time to facilitate the early DFX processing and shell design. The front and back design drawings and three-dimensional design drawings are shown in Figures 7 and 8.

Figure 7 3D schematic diagram of the domain controller PCB

Figure 8 Domain controller hardware physical picture

3 Domain Controller Software Design

G9X is divided into SAFETY domain and AP domain according to different resources. SAFETY domain is the Cortex-R5 core processing domain, equipped with FreeRTOS real-time operating system, mainly responsible for processing information with high real-time requirements such as CAN and LIN; AP domain is the Cortex-A55 core processing domain, equipped with Linux rich operating system, mainly responsible for processing network-related information, such as DOIP, OTA, etc. The overall architecture of domain controller and gateway controller software is shown in Figure 9.

Figure 9 Overall software architecture

The domain controller body-related functions are implemented by the real-time working core Cortex-R5, and its software architecture refers to the specific application functions in the application layer. The real-time operation layer is the middle layer between the application layer and the underlying driver, which implements the interface and logical conversion with the application layer and the driver layer. The driver layer mainly implements the access control of hardware devices. The domain controller body control function is a 10ms periodic running task, and the simplified task workflow is as follows. The RTE software architecture is shown in Figure 10.