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Panta STM32H750 Part 5 (Using the timer to generate a specified number of PWM pulses) [Copy link]

The author used PWM to output a specified number of pulses in his previous projects, and happened to try it on H750. He generated the specified number of pulses and used cubemx to generate code, which was very convenient to develop.

The author of this post simply uses two methods to output the specified number of pulses. The first is to use the RepetitionCounter to get the number of pulses, but this solution can only output a maximum of 255 pulses because the maximum number of repetition counters is 255. The second is to use PWM+interrupts to determine whether the PWM number has reached the specified number of pulses in the interrupt and stop PWM output when the number of pulses is reached. This content is originally created by RCSN


, a netizen on the EEWORLD forum. If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source

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I've come across similar applications before, the OP is awesome! I don't know if you can share the source code   Details Published on 2020-9-16 10:12
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Let’s talk about the first method first, which uses a repetitive counter to output a specified number of pulses. This method can only be used in advanced timers or general timers.

Then generate the code directly. After generating, you need to add a code yourself.

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Through the above two callback interfaces, the first one is to determine whether the specified PWM output is completed, and internally determine whether the number of times reaches the pulse number. The second callback is the counter overflow update, which updates the indication that the repeat counter has overflowed the specified count number downward or upward, which can be used as a pulse output number to determine whether the number of pulses is completed.

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After writing, after burning into the board, it is found that there will be a small pulse at the beginning or end, which is not allowed for precise control of related devices.

Later I found that the oscilloscope input internal resistance was large, and the IO output was normal after adding internal pull-up. PWM output requires hardware pull-up and pull-down.

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This way of using software has too much overhead, and an interrupt is required after each pulse, and high-frequency pulses are not possible.

If you use a Slave Timer to generate PWM, and another Master Timer to gate it (OPM mode), you can calculate the time and get it done in one go.

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When the number of pulses does not exceed 255, use the single pulse mode, only one interrupt is needed, and there is no need to set up a timer trigger. However, if the number of pulses exceeds 255, your solution is suitable.  Details Published on 2019-11-21 08:15
When the number of pulses does not exceed 255, use the single pulse mode, only one interrupt is needed, and there is no need to set up a timer trigger. However, if the number of pulses exceeds 255, your solution is suitable.  Details Published on 2019-11-21 08:06
 
 
 

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cruelfox posted on 2019-11-21 07:55 The software overhead is too high. An interrupt is required after each pulse, and high-frequency pulses cannot be achieved. If a slave timer is used to generate PWM, another...
When the number of pulses does not exceed 255, use the single pulse mode, only one interrupt is required, and there is no need to set up another timer trigger. However, if the number of pulses exceeds 255, your solution is suitable
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cruelfox posted on 2019-11-21 07:55 The software overhead is too high. It has to be interrupted after each pulse, and high-frequency pulses cannot be achieved. If a slave timer is used to generate PWM, and another...
I think h750 has up to 18 + timers. Using a timer as a master is actually not a big deal. I will find time to post a post to use cubemx to generate this solution.
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For RC complementary outputs, if both pins are stopped, will the voltage levels be low?

For example, in the BUCK synchronous rectification circuit shown below, if VT and SR are PWM complementary outputs, the circuit works normally. Now, if you want to make the circuit not work, and both VT and SR are in the cut-off state, how should it be configured and operated?

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It does not have to be all low, it can be configured according to the PWM mode and PWM polarity. To set it to PWM output or fixed level output, just enable or disable the counter respectively.  Details Published on 2019-11-21 14:28
 
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chenzhufly posted on 2019-11-21 12:41 RC complementary output, if both pins are stopped, will the voltage level be low? For example, the BUCK synchronous rectifier circuit in the figure below, ...

It does not have to be all low, it can be configured according to the PWM mode and PWM polarity. To set it to PWM output or fixed level output, just enable or disable the counter respectively.

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I have come across similar applications before, the host is awesome

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RCSN posted on 2019-11-21 14:28 It doesn't have to be all low, it can be configured according to the PWM mode and PWM polarity. To set it to PWM output or fixed level output, enable or disable it respectively...

I've come across similar applications before, the OP is awesome!

I don't know if you can share the source code

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