Analysis of ACMC technology's working principle, advantages and application in automotive infotainment

The increasing power requirements of high-performance microprocessors in automotive multimedia information processing (e.g., infotainment products) have led to many design issues such as interference immunity, EMI, and loop compensation. Average current-mode control (ACMC) can help solve these problems, especially in automotive infotainment applications. This article describes ACMC in detail and shows the advantages of current-mode control-based designs for infotainment applications. We use the MAX5060/MAX5061 as an example to illustrate the working principle of ACMC and supplement the content provided in the data sheet.

Define design goals

Each specific automotive infotainment terminal will have a unique set of technical and commercial requirements for power management. The most important design considerations include efficiency, size, EMI, transient response, design complexity and cost. All parameters are indirectly related to the switching frequency of the power supply. The selection of this important parameter can achieve a reasonable compromise between the above requirements.

Advantages of ACMC

For high current output (5A to 25A) converters, reducing the current sense resistor in the current mode control (CMC) technique helps improve efficiency. Here, CMC refers to the fixed frequency operation mode with peak current sensing. However, there is a disadvantage to this approach: CMC makes the converter very sensitive to noise. When the current is large, even the best PCB layout cannot completely suppress the noise superimposed on the current sense signal. To solve this problem, voltage mode control VMC can be selected, which is a traditional and proven technology. VMC improves anti-interference ability and conversion efficiency, but requires certain loop compensation design to achieve acceptable performance indicators.

ACMC Design Basics

ACMC technology combines the interference immunity and efficiency of VMC with the stability of CMC. Figure 1 shows the functional block diagram of the ACMC buck converter.

To better understand ACMC, let's first review the principles of CMC. Observe Figure 1. If the current error amplifier (CEA) and sawtooth generator are removed, the output of the current sense amplifier will be connected to the inverting terminal of the PWM comparator, and the output of the voltage error amplifier (VEA) will be connected to the non-inverting terminal. The result is a dual-loop system that controls the inductor current (inner loop) and the output voltage (outer loop).

As mentioned above, in high current output applications, it is desirable to make the current sense resistor RS (see Figure 1) as small as possible to reduce the power consumption of the converter. However, the result of doing so is to introduce a weak signal into a noisy environment, which appears as jitter in the system.

In the ACMC structure, the current sense signal is fed into the inverting input of the CEA (Figure 1), while the VEA regulates the inductor current at the non-inverting input of the CEA. By compensating the CEA through the feedback network, a series of operations can be completed: adjusting the current sense signal to obtain maximum DC gain (for a buck converter, the DC current of the inductor is equal to the output current of the converter); allowing the actual current sense signal to pass through the amplifier unimpeded; and finally, suppressing the high-frequency switching noise superimposed on the signal. The high DC gain of the CEA allows this control scheme to accurately control the output current. The flat gain of the current sense signal by the CMC will cause peak and mean errors in the current when the input voltage changes. As shown in Figure 1, the output of the CEA is compared with the ramp voltage to generate a desired PWM signal to drive the power MOSFET.

Figure 2 shows the control waveforms of Figure 1. Note that the inductor current signal iL (red) compared to the sawtooth wave is inverted. The SR latch after the PWM comparator avoids signal transitions caused by noise. Similarly, the clock signal resets the sawtooth ramp voltage, essentially eliminating the possibility of prematurely turning off the MOSFET due to noise spikes. Another feature of this control architecture is that no ramp voltage compensation is required when the duty cycle exceeds 50%, because the sawtooth ramp signal already provides this compensation.

For the buck converter shown in Figure 1, the inner loop is used to compensate for changes in input voltage. As the input voltage increases, the slope of the CEA current signal becomes steeper (Figure 2), which narrows the duty cycle. The outer loop is used to compensate for output voltage changes caused by load changes. Since the inductor current is processed by the VEA, the power supply exhibits a single-pole response, simplifying the voltage compensation loop.

CEA compensation is very simple, and the MAX5056/MAX5061 data sheet provides the guidelines to follow. The MAX5060/MAX5061 DC-DC converters address the above design issues and are highly efficient, low-noise, and cost-effective. Figure 3 illustrates the CEA architecture with the compensation network in the device. This compensation network is recommended because the CEA does not provide direct access to its inverting input. Note: The CEA is a transconductance amplifier and has a higher output impedance than a standard op amp.

To optimize the current loop, the falling slope of the inductor current iL (red signal in Figure 2) will follow the slope of the sawtooth voltage, and iL cannot exceed the ramp voltage, otherwise resonance and instability will occur.

Ignoring the voltage drop of the synchronous rectifier, the inductor current falling slope of the buck converter can be given by:

The maximum input voltage of the IC is 28V. If the converter needs to withstand voltages up to 72V, the circuit in Figure 5 is recommended. This circuit also provides reverse input voltage protection.

2. Synchronous switching frequency

Synchronizing switching frequencies is an important step in infotainment systems to prevent interference from the DC-DC converter to sensitive loads, such as car radio systems, TV tuners, displays, and navigation systems. These devices achieve synchronization by operating the DC-DC converter in self-oscillation mode and then synchronizing it to the required frequency using a high-performance processor. The MAX5060/MAX5061 operate in a synchronizable oscillation frequency range of 125kHz to 1.5MHz.

If synchronizing the MAX5060/MAX5061 to an external clock is not feasible or the converter's switching frequency generates excessive EMI, a spread-spectrum oscillator, such as the DS1090U-16 spread-spectrum oscillator, shown in Figure 6, can be used to drive the SYNC pin. In this example, external resistors on the DS1090U-16 set the frequency to 300kHz, with a frequency dither range of ±4%, or 12kHz. The dither ratio should not be too high because the spread spectrum will cause a phase shift in the system loop that needs to be compensated. For more information on frequency calculations for the DS1090, refer to Application Note 3692: DS1090 Frequency Calculator.

3. Step-up/step-down operation

The MAX5060/MAX5061 can also perform step-up or step-down conversion (Figure 7).

Note: Capacitors C1 and C2 in Figure 7 need to withstand larger ripple currents than a buck converter with the same output current. In addition, the two inductors in the figure can be wound with the same core, with the same-named ends of L1 and L2 as shown in Figure 7. If separate inductors are used, the winding direction issue can be ignored.

The CSA common-mode range of the MAX5060/MAX5061 can be extended to 0 to 5.5V. When designing a converter with an output voltage greater than 5V, the following two circuits can be used. The circuit in Figure 8 uses an off-the-shelf current-sense transformer, and the circuit in Figure 9 uses a resistor bridge. 1% resistors are used for the design, and VRS is biased at 5V to reduce the size and power consumption of resistor kRS. The EAN input should be set to 0.6V, requiring a separate voltage divider.

in conclusion

Although CMC DC-DC converters have been favored by designers, the requirement to provide high-efficiency conversion using inexpensive current-sense resistors has exposed a major drawback of CMC: sensitivity to noise. The ACMC technology used in the MAX5060/MAX5061 solves the problem of noise sensitivity. ACMC enables DC-DC converter designs to meet the requirements of high-performance microprocessors, especially high-performance microprocessors in automotive multimedia terminals.