Motor control using three different dV/dt control methods

Introduction

In some applications such as motor control, it is important to slow down the dV/dt during switching. Too fast a speed will cause voltage peaks on the motor, which will damage the winding insulation and shorten the motor life. In this application note, Dr. Zhongda Li, senior R&D engineer from UnitedSiC, compares three different dV/dt control methods.

dV/dt Switching

The traditional approach to reducing the switching dV/dt of silicon MOSFETs, IGBTs, and SiC MOSFETs may be to increase the external gate resistor value. Because the CGD (CRSS) of these devices is relatively high, the external RG value can slow down the dV/dt without excessive delay time. This approach is very good for fast switching applications such as totem pole PFC, where faster dV/dt results in lower switching losses. However, for slower applications such as motors, it may require very high resistor values. Slowing it down to 5-8V/ns may require a gate resistor of several kiloohms, which may result in excessive switching delay time, resulting in slow step rates. For position control applications, this may cause performance to suffer. There are methods to effectively control the dV/dt of SiC FET devices from 45V/ns to 5V/ns without excessive delay time. The three methods are: external gate-to-drain capacitance, device RC snubber circuit and JFET direct drive, which require the use of UnitedSiC 9mΩ 1200V SiC FETs in a standard TO247-4L package (UF3SC120009K4S) and switching at 75A/800V.

External gate-drain capacitance

The first method is to add external gate-to-drain capacitance (CGD) between the gate and drain of the high-side and low-side FETs of the half-bridge. For the selected SiC FETs, the value of CGDEXT was chosen to be 68pF. We intentionally added a 20nH parasitic inductance in series with the external capacitors to illustrate that this method is insensitive to parasitic inductance in the path (Figure 1).

[Figure 1 Gate drive with external CGD (on both high-side and low-side FETs) for dV/dt control] In a real application using standalone devices, this parasitic inductance should be much less than 20nH, because the external CGD may be placed close to the FET on the circuit board. However, if the UnitedSiC FET chip is used inside the module and the external CGD is placed outside the module, there may be a parasitic inductance of 20nH in the path. We first optimized the external CGD method through SPICE simulation using the UF3SC120009K4S SPICE module, and then experimentally verified it using a double-pulse test circuit. The 68pF external CGD was intentionally soldered between the C and D pins of the TO247-4L instead of on the circuit board to increase the parasitic inductance in the path. The turn-off and turn-on waveforms obtained from the experimental measurement and SPICE simulation are superimposed for comparison. In Figure 2, the measured waveforms and the simulated waveforms are very consistent.

[Figure 2 Overlay of turn-off (left) and turn-on waveforms of experimental measurement (solid line) and SPICE simulation (dashed line) (75A, 800V, external CGD of 68pF, RG of 33Ω)] With an external CGD of 68pF, dV/dt can be effectively controlled in the range of 25V/ns to 5V/ns using an RG of 10Ω to 33Ω. For both SPICE and experiment, EON and EOFF are obtained by calculating IDS×VDS during the turn-on and turn-off transitions, which increase with RG as expected. The reason why the external CGD can tolerate high parasitic inductance (20nH in SPICE) is that the current during switching is very small. For the case of an external CGD of 68pF and a dV/dt of 8V/ns, the estimated current is only 0.54A and is consistent with the current in the SPICE simulation. Therefore, it is suitable for modules, where the external CGD is placed outside the module, on the board gate drive, and there is some parasitic inductance in the path.

Device RC Snubber Circuit

The second dV/dt control method places an RC snubber circuit in parallel with the high-side and low-side switches. We intentionally placed a 20nH parasitic inductance in series with the snubber circuit to demonstrate that parasitic inductance can be tolerated in the snubber circuit path for this method (Figure 3).

[Figure 3 RC snubber circuit in parallel with FET (including high-side and low-side FET) to achieve dV/dt control] In real applications using independent devices, the RC snubber circuit may be very close to the FET and the parasitic inductance is only a few nH. However, if the UnitedSiC FET chip is used in the module, the RC snubber circuit can be placed outside the module and there may be 20nH parasitic inductance in the path. The turn-off and turn-on waveforms obtained from experimental measurements and SPICE simulations are superimposed for comparison (Figure 4). Note that the IDS current in the chart includes the snubber circuit current. Experiments and SPICE simulations show that dV/dt can be effectively controlled in the range of 50V/ns to 5V/ns by C_SNUBBER (snubber circuit capacitor) up to 5.6nF.

[Figure 4 Overlay of turn-off (left) and turn-on waveforms of experimental measurement (solid line) and SPICE simulation (dashed line) (75A, 800V, RC snubber circuit is 0.5Ω, 5.6nF)] The switching losses (EON, EOFF and ESW) are obtained by calculating IDS×VDS during the switching transition, where IDS includes the snubber circuit current. Therefore, the snubber circuit losses are included in EON and EOFF. However, the snubber circuit losses on the 0.5Ω R_SNUBBER are very low, especially when the dV/dt is slow. At C_SNUBBER of 4nF and turn-off dV/dt=8V/ns, SPICE shows that the snubber circuit losses are only 0.2mJ, or 2W at switching f=10kHz. We found that the snubber circuit can also tolerate high parasitic inductance (20nH in SPICE), so if a module form is used, the RC snubber circuit can be placed outside the module.

JFET direct drive

The third method is direct drive, in which case the Si MOS is turned on only once, after the circuit is started, and the JFET gate is switched directly between -15V and 0V (Figure 5). In this configuration, normally-off operation is retained, but gate PWM and a simple “enable” signal are required.

During the switching transient, the high-side JFET remains off and the voltage is -15V, requiring synchronous rectification to allow the freewheeling JFET to minimize conduction losses in the third quadrant.

[Figure 5 JFET direct drive method (both on high-side and low-side FETs) to achieve dV/dt control] Because SiC JFETs have considerable CRSS (CGD), a small RG of 4.7Ω is sufficient to slow down dV/dt to 5V/ns. The turn-off and turn-on waveforms obtained from experimental measurements and SPICE simulations are superimposed for comparison (Figure 6).

[Figure 6 Overlay of the turn-off (left) and turn-on waveforms of experimental measurement (solid line) and SPICE simulation (dashed line) (75A, 800V, JFET direct drive and RG of 4.7Ω)] The IDS current waveforms between the SPICE (dashed line) and experimental (solid line) waveforms are in good agreement. However, the experimental VDS waveform shows that its dV/dt is slower than the SPICE waveform. The reason may be that the JFET gate driver used in the experiment cannot provide enough gate current to charge and discharge the JFET CRSS during the dV/dt transition, resulting in a slower dV/dt. Comparing the dV/dt obtained by SPICE and the measurement, it is found that the dV/dt can be well controlled between 15V/ns and 4V/ns. Using the same approach as the previous two methods, the switching losses can be obtained, and EON and EOFF increase with the JFET RG as expected.

Comparison of three dV/dt control methods

The three methods were compared using SPICE simulations under the same restriction of dV/dt ≤ 8V/ns (Figure 1).

[Table 1 SPICE simulated performance of 75A/800V switch when dV/dt is equal to 8V/ns maximum]

The JFET direct drive approach exhibits the lowest overall switching losses at 9.02mJ. This approach requires a negative voltage to drive the SiC JFET and requires an enable signal to the Si MOS at circuit startup, which increases the complexity of the gate drive compared to the other two approaches. Standard UnitedSiC FETs do not provide access to the JFET gate, but a new dual-gate TO247-4L product is in development that has both a SiC JFET gate and a Si MOS gate, and is suitable for JFET gate drive. This approach is also suitable for modules, where a separate JFET gate pin can be added. As shown in this study, the JFET gate path can tolerate reasonable parasitic inductance (20nH in SPICE), so the JFET gate driver can be placed on the gate drive circuit board on top of the module. The external CGD and device RC snubber circuit approaches exhibit higher switching losses, but they do not require access to the JFET gate. Both approaches can be easily implemented on the circuit board when using UnitedSiC FETs in a standalone package such as TO247. Since both methods can tolerate reasonable parasitic inductance (20nH in SPICE), they are also suitable for modules with UnitedSiC chips inside. One disadvantage of the RC snubber circuit method is that it cannot adjust the turn-off and turn-on dV/dt separately. As shown in Table 1, to achieve a turn-on dV/dt of 8V/ns, the turn-off dV/dt must be reduced to 4V/ns, which will increase EOFF. However, the external CGD and JFET direct drive methods use separate RGON and RGOFF, which can be adjusted separately. As shown in Table 1, by optimizing RGON and RGOFF separately, both the turn-on and turn-off dV/dt can be 8V/ns.

Summarize

In summary, good dV/dt control can be achieved using these simple techniques. The two advantages of UnitedSiC FETs, lower conduction losses and short-circuit robustness, are extremely important for efficient and reliable motor drive applications.