Design of CAN interface of LPC2131 based on CPLD

introduction

Philips' LPC2131 is a high-performance 32-bit RISC microcontroller based on ARM7TDMI-S. It has all the advantages of ARM processors - low power consumption, high performance and relatively rich on-chip resources, but LPC2131 does not have an integrated CAN controller and cannot use the CAN bus for communication. In order to enable LPC2131 to communicate using the CAN bus, its functions can be realized through external expansion. At present, the more common method is to use a CAN controller to design a CAN bus interface outside the LPC2131. The interface circuit between LPC2131 and the CAN controller is shown in Figure 1.

In this method, LPC2131 is connected to CAN controller SJA1000 through GPIO port to realize data exchange. LPC2131 sets the high/low state of I/O port through register IOSET/IOCLR. Although the selected pins can be set/lowed at the same time, some lines cannot be pulled high and some lines cannot be pulled low at the same time. Assuming that the initial state of P0[15:8] is 0xa5, if P0[15:8] is changed to 0x5a at the same time, it must be done twice through IO0SET and IO0CLR. The program is implemented as follows:

PINSEL0 = 0x00000000;

IO0DIR = 0x0000FF00;

IO0SET=0x5a00;

IO0CLR=0xa500;

An intermediate state of 0xFF will appear on P0[15:8]. In high-speed communication systems, these intermediate states may cause losses. Although such intermediate states can be eliminated by operating the IO0PIN, Philips does not recommend this practice and should not be used unless necessary.

The CAN driver interface chip and the serial port interface of LPC2131 are matched at the level, so in theory, the two can be directly connected and implemented by serial communication. When using CAN bus communication, terminal resistors should be added at both ends of the CAN bus during long-distance communication. Its function is to prevent data transmission from being reflected back and generating reflected waves that damage the data; at the same time, it can improve the anti-interference ability of bus transmission. In theory, when sampling at the midpoint of each received data signal, as long as the reflected signal is attenuated to a low enough level at the beginning of sampling, matching can be ignored. The usual judgment principle is to match according to the data rate and cable length, but this is difficult to grasp in practice, and is generally designed based on experience.

Programmable logic device (PLD) is a new type of logic device developed in the 1970s based on ASIC design. In the late 1980s, Altera and Xilinx of the United States launched large-scale and ultra-large-scale complex programmable logic devices (CPLD) and field programmable gate array devices (FPGA) respectively. Since the 1990s, programmable logic devices have developed rapidly, moving towards high integration, high speed and low price; their application areas are constantly expanding and can be used in many aspects such as state machines, synchronization, decoding, counting, bus interfaces and serial-to-parallel conversion. Using CPLD can improve system integration, reduce noise, enhance system reliability and reduce costs.

The emergence of CPLD technology provides us with an effective solution: connect a CPLD between the CAN driver interface and LPC2131, and program the CPLD to be responsible for serial bus data transmission and prevent CAN send reflection.

The CPLD chip of Altera's MAX3000A series, model EPM3128ATC100-7 (abbreviated as "EPM3128"), is selected. This chip is compatible with 3.3 V and 5 V I/O ports. In this way, LPC2131, EPM3128 and TJA1040 are matched with each other in terms of I/O level. [page]

1 EPM3128 Interface Definition

EPM3128 is set as a bidirectional serial bus channel. Among them, two I/O ports are defined as CANRXD (IN) and CANTXD (OUT), which are connected to the RXD and TXD terminals of the CAN transceiver TJA1040 respectively, forming the receiving and sending data channels on the CAN bus; the other two I/O ports are defined as ARMRXD (IN) and ARMTXD (OUT), which are connected to the RXD1 and TXD1 terminals of the LPC2131 respectively, forming the receiving and sending data channels of the processor's serial port. During the entire data transmission process, the protocol and format of the serial data are not changed, and the interface circuit is all TTL level, so no processing is required. The verification and error reporting of the communication data are completed by the processors at both ends of the communication. The interface block diagram of LPC2131, EPM3128 and TJA1040 is shown in Figure 2.

2 EPM3128 Function Implementation

Figure 3 is the internal logic of EPM3128 data transmission and shielding CAN transmission reflection using function block programming. In the figure, txArm2 and rxCan2 are defined as input variables, corresponding to the external ARMTXD and CANRXD pins respectively; txCan2 and rxArm2 are defined as output variables, corresponding to the external CANTXD and ARMRXD pins respectively. When the bus is idle, the state on the bus remains "1", that is, the values ​​of txArm2, rxCan2, txCan2, and rxArm2 are all "1". When the input bus receives a state "0" signal, it means that the bus starts to transmit data. If LPC2131 wants to send data, LPC2131 first sends a "0" start signal to the ARMTXD port, occupies the bus and starts sending data frames at the next clock; if TJA1040 receives new data from the field, TJA1040 first sends a "0" start signal to the CANRXD port, occupies the bus and starts sending data frames at the next clock. In this way, the transmission of data bits from serial port to serial port during normal communication is completed.

The program shields the CAN transmission reflection, that is, shields the "0" signal reflected from the output bus received by the CAN bus, because the interface is awakened from the high-impedance state by a "0" start signal. If LPC2131 is sending data, the input port ARMTXD transmits a "0" signal to the variable txCan2 through the variable txArm2, and sends it out from the output port CANTXD. Affected by the bus radiation, the CANRXD input port will receive a "0" signal from the CAN bus and transmit the "0" signal to the variable rxCan2. At this time, the "0" signal received by rXCan2 is an error signal. After logical judgment, the program maintains the variable rxArm2 as 1, and the port ARMRXD still maintains the high-impedance state "1". Although the reflected "0" signal is received, it is shielded and processed inside the CPLD. If it is not shielded, then this erroneous "0" signal will wake up the receiving bus from the high-impedance state, directly affecting the data communication. The purpose of the D flip-flop in the program is twofold: one is to cache input and output and smooth out signal glitches; the other is to implement control signal functions, such as output reset and synchronization. [page]

Compile the program with QuartusII software and simulate it with the simulation tool. As shown in Figure 4, the baud rate is 115 200 bps, edit the waveforms of the input points txArm2 and rxCan2, and check the waveforms of the output points txCan2 and rxArm2. To facilitate image recognition, set the time parameter occupied by data port transmission to 0 in the simulation.

First, the validity of the output waveform is demonstrated. Observing the waveforms of txCan2 and rxArm2 in Figure 4, it can be seen that the values ​​at all times are certain, which proves that the system is in a stable state and the waveform is valid.

Then, the logic of the output waveform is demonstrated. According to the logic design of the program, the data transmission of the txArm2 channel has priority, and txCan2=txArm2 is always maintained. From the simulation results, it can be seen that the waveform of txCan2 is exactly the same as that of txArm2; when the txArm2 channel is "0", the data input by rxCan2 is shielded, and the output of rxArm2 is always kept as "1". Observing the waveforms of all inputs/outputs at any time in Figure 4, it can be seen that the simulation results are correct.

Finally, verify the timing of the output waveform. This part of the program is a combinational logic design, that is, all outputs change with the corresponding input changes. As shown in Figure 4, the timing of the simulation results is correct.

Conclusion

This paper implements serial communication between LPC2131 and CAN bus based on CPLD technology. This method is simple to implement and has good stability. It is suitable for multi-channel serial communication systems using CAN bus. This technology has been applied in practice and has been tested in practice.