NAND flash memory has been around for so many years, and its development has never stopped. Basically, it has been pursuing higher storage density. Therefore, from the initial SLC to the current QLC, although the storage density has been greatly improved, in terms of performance, the original SLC is still faster. At the 2020 Flash Memory Summit, Andy Hsu, CEO and founder of NEO Semiconductor, introduced their company's new X-NAND flash memory architecture, which is expected to combine the speed of SLC with the high density and low price of QLC.
The news comes from tomshardware, which claims that X-NAND's random read and write are three times faster than QLC flash memory, continuous read is 27 times faster, and continuous write is 14 times faster. In terms of performance, it is indeed very fast.
In addition, the chip size is smaller, and the die size is only 37% of the same 16 planes NAND flash memory, which allows better flexibility and can reduce the chip size according to actual needs. Moreover, X-NAND still has high parallelism in a smaller size, just like what you see on smartphones or M.2 SSDs. This can be achieved without affecting durability and cost, and its power consumption is very low.
Today's QLC SSDs rely heavily on SLC Cache, because the original write speed of QLC is too low, so QLC SSDs basically use its capacity advantage to equip large-capacity SLC Cache. In the consumer market, the write pressure is usually not very high, so there is enough free time to move the SLC buffer to the QLC flash memory for storage, but there is no such time for enterprise-level loads. X-NAND allows SLC and QLC write modes to be performed simultaneously, so that the flash memory can always maintain the performance of SLC.
Western Digital predicts that QLC's share of the flash memory market may be as high as 50% by 2024. The design goal of X-NAND is to ensure the use of existing NAND solutions. Traditional NAND processes do not require structural changes, have no additional manufacturing costs, and can be developed through rapid sampling. The design aims to accelerate the promotion and application of QLC, especially in the data center market, so that QLC performance is no longer a bottleneck.
At the same time, X-NAND has modified the programming and erasing strategies to improve the durability of QLC flash memory. X-NAND changed the page buffer from 16KB to 1KB, but the size of the Plane can be increased by 16 times.
Plane is the smallest unit of flash memory. There is one or more Planes in each Die. The page buffer stores the data stored between the bus and the flash memory. Flash memory chips are divided into Planes that protect bit lines or cell strings, so Plane division can reduce the length of the bit lines, which helps improve performance. This technology can be further enhanced by shielding between adjacent bit lines to reduce the setup time when reading or verifying programming. Since up to sixteen bit lines can be programmed in parallel, write performance is improved.
X-NAND has six main features: multi-bitline write, multi-plane QLC programming, program suspend, multi-BL read, single latch QLC read, and SLC/QLC parallel programming. Depending on the implementation, the program throughput can be greatly improved because multiple planes can be used in the programming sequence.
Using multiple banks allows for simultaneous SLC and QLC programming, ensuring that SLC pages are never full while data can be transferred to QLC pages at SLC speeds. Programming allows for the use of internal shared inter-page buffer data lines or I/O buses to minimize additional latency. Reads are improved by using Plane latches to read each bit line, and data can be refreshed in a non-destructive manner like DRAM.
X-NAND can be used with any number of existing NAND, which increases flexibility and simplifies conversion. NEO Semiconductor hopes that the technology will be cost-effective, fast and easy to implement in existing designs. The company said it is particularly useful for high-density flash memory like QLC because it can take advantage of high capacity, high performance and small chip area, while having good endurance and power consumption. The technology targets embedded devices, AI and cloud, including NAS, data centers and edge computing.
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