Design of graphics capture card based on dual memory

    Abstract: This paper proposes a new design of an image acquisition card, which uses two memories to be used alternately, so that image acquisition and computer reading of image data can be carried out at the same time, improving image quality. The defects of general image capture cards are analyzed, and the design ideas and principles of new image capture cards are given.

    Keywords: image acquisition, upper memory, computer

    Digital image processing technology is increasingly widely used in many fields. Microcomputer image processing systems are widely used in medical, meteorological, industrial vision and other fields due to their flexible use and high cost performance. In industrial control, cameras are generally used to obtain on-site images, but now the signals output by cameras are mostly analog signals. In order to realize the interface between the camera and the computer, an image capture card must be used.

    However, the image acquisition cards currently on the market often cannot collect data and read data at the same time, which brings great trouble to programming and real-time control. The image card provided in this article solves this problem. It uses two pieces of memory. The memory read by the computer and the memory used for image acquisition are used alternately, so that image acquisition and data reading by the computer can be carried out at the same time.

    This article first analyzes the defects of general image capture cards, and then gives the principles and design ideas of new image capture cards. Since this frame grabber is based on the full TV signal, it is necessary to briefly introduce the black and white full TV signal.

1 Full TV signal and its principles

    The black and white CCD camera converts the image (light signal) into an electrical signal through photoelectric conversion, and its final output signal is a black and white full TV signal. It mainly consists of image signal (video signal), composite blanking pulse and sync pulse.

    The polarity of TV signals can be divided into positive polarity and negative polarity image signals. If the image is the brightest, the corresponding signal voltage has the largest amplitude, then the signal is called a positive polarity signal; otherwise, it is a negative polarity signal. Negative polarity signals are used here. The image signal is sent to the video amplifier for amplification and processing, and at the same time, the horizontal and vertical synchronization pulses and horizontal and vertical blanking pulses sent by the synchronizer are added to form a full TV signal.

    The blanking pulse is mainly used to eliminate the retrace lines generated during the reverse path of horizontal and field scanning. The synchronization pulse ensures that the scanning points at the receiving end and the originating end should have a one-to-one corresponding geometric position.

    Since there is no horizontal synchronization signal during field synchronization, this affects strict synchronization throughout the scanning process. In order to solve the entire problem, the method of slotting in the field synchronization pulse is used to replace the synchronization signal. The pulses twice the horizontal frequency before and after the field synchronization are called equalization pulses.

    TV standards stipulate that the amplitude ratio of the entire TV signal is: if the peak white level to the sync level is taken as 100%, then the value from the peak white level to the blanking black level is 75%, and the peak white level is 0%, the image signal is between white and black levels.

    The signal is shown in Figure 1. From a time perspective, 25 frames of images are transmitted per second, with 625 lines per frame; during interlaced scanning, there are 50 fields per second, and 312.5 lines per field. The period of each line is 64μs, of which the image takes up 52.2μs and the line blanking takes up 11.8μs. The horizontal synchronization pulse is 4.7μs, which is delayed by 1.3μs than the horizontal blanking. The period of each field is 312.5H=20ms, in which the field blanking signal accounts for 25H+1 line blanking signal, which is equal to 1600μs+11.8μs. The width of the equalization pulse is 2.35μs, and the period is half a line, with a total of 12 pulses (the first 6 and the last 6). The width of the field sync pulse is 2.5H time, which is 160μs. The field synchronization pulse has 6 groove pulses and its width is 4.7μs.

    In the full TV signal, the leading edge of the odd-numbered field sync signal is used as the starting point of one field. Lines 1, 2, and 3 are field sync signals, lines 4, 5, and 6 are post-equalization pulses, and lines 7 to 22 are still field cancellations. The blanking signal of this field starts from line 623 of the previous field. Therefore, the entire blanking signal is 25 lines plus the blanking time of one line. The image signal appears from line 23 to line 309.5, a total of 287.5 lines. This is the first field or odd field. Starting from line 309.5 is the field blanking signal and pre-equalization pulse of the next field. The synchronization pulse of the next even field appears at line 312.5. The odd number ends here and the even field begins. An odd field plus an even field together is called a frame.

2 Principles of general image capture cards

    The structure of a general image acquisition card is shown in Figure 2.

    First, the video signal is preprocessed and synchronously separated. Preprocessing mainly includes amplification, brightness, contrast adjustment, and signal limiting (protecting A/D). The synchronization separation circuit mainly separates the horizontal synchronization and field synchronization signals in the signal for use by the timing circuit of the acquisition card. Then the processed video signal is converted into a digital signal by a high-speed A/D converter, and written into the memory under the control of the timing circuit.

    But there is a problem with such a capture card. Data collection and data reading cannot be performed at the same time. It may be assumed that during the odd-numbered field scanning period, the A/D conversion result is stored in the memory every time a sample is taken. During the even-numbered field period, the computer reads the data in the memory into the computer. However, when the computer reads the memory, the results of the A/D conversion cannot be written to the memory at the same time, that is, the memory cannot perform both reading and writing operations at the same time, so the even field information will be lost.

3 Design of image capture card based on dual memory

    In order to solve this problem, two pieces of memory are used to work alternately. When data is written to one piece of memory, the computer reads data from the other piece of memory, and vice versa. The block diagram of this capture card is shown in Figure 3. Each part of the circuit is introduced below.

    (1) Preprocessing circuit: realizes the conversion of standard full TV signals into 0~5V analog signals, and has functions such as brightness adjustment and contrast adjustment. The operational amplifier used in the amplifier adopts wideband operational amplifier LM318.

    (2) Synchronization separation circuit: In order to store the digitized image signal into the corresponding frame memory, the horizontal synchronization signal and the field synchronization signal must be obtained. Since the synchronization signal has the largest amplitude, accounting for 76% to 100% of the total TV signal amplitude, the amplitude separation method can be used to separate the composite synchronization signal based on this feature. And because the width of the field synchronization pulse is 160μs, which is much larger than the width of the horizontal synchronization pulse of 4.7μs, the row synchronization and field synchronization can be further separated from the separated horizontal and field composite synchronization signals.

    (3) A/D converter: The A/D converter in the image capture card is completed with the 8-bit high-speed video conversion chip CA3318CE. Its maximum conversion rate can reach 15MHz. From the previous analysis of the black and white full TV signal, it can be seen that each line of image takes about 52.2μs. This card needs to sample 512 points during the line of each line of the TV signal, and the sampling clock is about 10MHz. Therefore, choosing CA3318CE fully meets the requirements, and only needs to select its sampling rate at 10MHz.

    (4) Control circuit: The core device of the control circuit is a general logic gate array GAL20V8. This circuit generates the read signals MEMR1, MEMR2 and write signals MEMW1, MEMW2 of the frame memory as well as the working status signals PC/LOCAL and required by the image acquisition card! PC/LOCAL, the circuit principle is shown in Figure 4. U33 is a GAL20V8, it works in simple mode, pins 18~22 are configured as outputs, and the others are configured as inputs. Pins 1~6 are connected to the address lines PC_A4~PC_A9 of the PC, pins 7~10 are connected to the address lines PC_A16~PC_A19 of the PC, pin 11 is connected to the system clock CLK, pin 1 3 Connect to PC_IOW signal, pin 14 is connected to the PC/LOCAL signal, pins 15 and 16 are connected to the blanking and vertical blanking indication signals H_MR and V_MR respectively, pin 17 is connected to the PC's read memory signal PC_MEMR, pin 1 8, 19 Writing of output frame memory RAM1 The signal MEMW2 and the read signal MEMR2, pins 20 and 21 output the write signal MEMW1 and the read signal MEMR1 of the memory RAM1, and the pin 22 outputs the signal PC/LOCAL_CLK as The clock of flip-flop OP6B, pin 23 is connected to the PC_AEN signal of the PC.

    The control circuit also generates PC/LOCAL signals. This signal must be controlled by PC. Here, the PC / LOCAL is the lowest as the PC I / O port. The mouth address is 220h to 22FH. The PC only needs to write 1 or 0 to 220h to 22FH. . The decoding of the I/O port address is completed by U33, which can be described in ABEL language as follows:

    IOCS=! (!PC_A4&PC_A5&!PC_A6&PC_A7&!PC_A8&PC_A9&!PC_AEN 

    PC／LOCAL_CLK＝IOCS#PC_IOW

    IOCS is the strobe signal of the port and is active at low level. When the PC's address lines PC_A9 ~ PC_A4 are 100010, PC_AEN is low level. When PC_AEN is high level, it indicates that the PC is in the DMA state. IOCS is valid. PC/LOCAL_CLK is generated by the OR of IOCS and the I/O port write address PC_IOW of the PC. When the port is not selected, it is always high; when the port is selected, it is generated by PC_IO W generates a rising edge. The rising edge of PC/LOCAL_CLK will trigger OP6B, latch the lowest bit data line PC_D0 of the PC, and generate PCLOCAL sum! PCLOCAL.

    When the address of the frame memory is generated by the PC, decoding logic is required. The memory space allocation for PCs below 1M is shown in Table 1. In order to avoid address conflicts, it can be seen from the table that the D0000H~DFFFFFH space can be used as the mapping address of the frame memory. This part of the decoding work is also completed by U33 and is described in ABEL language:

Table 1 Low-end memory space allocation of microcomputer

    MEMCS=! (PC_A19&PC_A18&!PC_A17&PC_A16

    It can be seen from the formula that when PC_A19 ~ PC_A16 is 1101, MEMCS is active (low level).

    The read signals MEMR1 and MEMR2 and the write signals MEMW1 and MEMW2 of the frame memory are also generated by the control circuit. When PC/LOCAL is 0, the PC reads the frame memory RAM1, and at the same time the AD conversion result is sent to the frame memory RAM2; vice versa. The read signal is generated by the PC's external memory read signal PC_MEMR and the decoding signal MEMCS; the write signal is generated by the system clock CLK, row and field blanking indication signals H_MR, V_MR. When either H_MR or V_MR is high level, it indicates that it is in the blanking state; only when H_MR and V_MR are both low level, it indicates that it is in field positive and row positive, and the result of A/D conversion is written into the frame memory.

    (5) Memory: For real-time collection and display, a memory is set in the digital image capture card. Generally, the image frame memory has the following requirements: A. high-speed access, B. large storage capacity, and C. asynchronous input and output access. The storage capacity necessary to store one frame or field of television signal can be calculated by the following formula:

    Storage capacity = number of scanning lines in one frame (or one field) × number of samples in one line × number of quantization bits

    In this image acquisition card, the image collected in one field is 512×256 points, which requires a memory with a storage capacity of 128K×8bit. As discussed in the previous hardware block diagram, two pieces of frame memory need to work alternately, that is, two pieces of 128K×8bit frame memory need to be set up to store the data information of odd fields and even fields respectively, so two pieces of high-speed static storage are selected. ChipSRAM 628128.

    The read signals MEMR1 and MEMR2 and the write signals MEMW1 and MEMW2 of the two frame memories are generated by the control circuit. The read signal is related to the PC's read memory signal PC_MEMR, while the write signal is related to the sampling clock of the image acquisition card! CLK related. The eight-bit data lines D0~D7 of the frame memory are connected to the data lines PC_D0~PC_D7 of the PC through the interface circuit.

    As mentioned above, the frame memory is mapped to D0000H ~ DFFFFFH, so the addressing range is only 64K, and the image data of one field is 128K, so address segmentation is used to achieve this, which can be achieved by performing I/O operations on the frame memory address line A16 accomplish.

    (6) Timing generation circuit: Mainly used to generate the scanning address signal of the frame memory required by the image acquisition card and the blanking signal to achieve synchronization and avoid row reversal.

    (7) Address switching circuit: This circuit is used to switch the scanning address signal generated by the timing generating circuit and the address signal of the PC. It is necessary to use a data selector to switch the address signal of the PC and the address signal of the acquisition card. Only four-bit data selectors can be found in general integrated circuits. If it is selected, 34 address lines will require nine pieces, which will take up too much space on the acquisition card, so GAL devices are used to implement it. Each GAL16V8 can achieve 8-bit data selection, while GAL20V8 can achieve 10-bit data selection, so 34 address lines only require 3 GAL16V8 and 1 GAL20V8.

    The image capture card has been produced and its tested performance fully meets the design requirements. This image capture card can be used in DOS operating system and Windows operating system. Due to the use of programmable logic devices, the number of chips is greatly reduced.

    Using a camera and a capture card as a sensor can solve many situations that conventional sensors cannot achieve. For example, in order to measure the height of the molten iron level in the sand mold during the automatic pouring process in the foundry, conventional liquid level sensors cannot withstand the high temperature of 1400°C. Even if there is such a sensor, because after a sand mold is poured, a new sand mold is delivered, and it is impossible to insert a liquid level sensor in each sand mold. By using a camera to capture the image of the sand mold sprue cup, and using a computer to process the image, the height of the molten iron level in the sand mold sprue cup can be calculated, thus solving the real-time control problem in the automatic pouring system.