LVDS Splitter Simplifies High-Speed ​​Signal Distribution

In recent years, with the increase in clock frequencies of microprocessors, DSPs, and digital ASICs, the data rate and bus throughput of backplane signals have also been steadily increasing in some emerging fields. The increase in speed has made the shortcomings of TTL single-ended signals such as high power consumption, jitter and high-level radiation more and more prominent. Although some reports believe that this standard speed can be maintained above 50MHz, due to the loss of transmission line impedance Problems such as matching and crosstalk and more difficult power supply decoupling force designers to seek more effective solutions.

A direct way to ensure the bandwidth of all buses and backplanes is to increase the bus width, but using this method will increase the difficulty of circuit board layout and require connectors with a very high number of pins, which will increase the system cost and is very bulky. When the distance exceeds a few centimeters, serial communication is an effective solution to the above problems. For high-speed communication systems, such as 3G base stations, routers, load/unload multiplexers and other equipment, great benefits can be achieved by using serial communication methods. In order to ensure that backplane communication has low bit error rate, low crosstalk and low radiation, low voltage differential signaling (LVDS) can usually be used to replace TTL signals.

1 Characteristics of LVDS, ECL, PECL, and CML

LVDS has been increasingly used in systems that require higher signal integrity, low jitter and higher common mode characteristics. It is one of the effective solutions currently used for high-speed serial interfaces. This solution is different from standards such as ECL, PECL, and CML. Among them, ECL is a traditional high-speed logic standard based on bipolar crystal differential pairs and uses a negative bias power supply. PECL is developed from the ECL standard and eliminates the negative power supply in the PECL circuit. The new generation of ECL devices has a delay time of about 200ps and can be used in systems with frequencies higher than 3GHz. Among existing interface standards, CML operates at the highest speed and can be used in systems with gigabit data rates. It also features an integrated 50Ω matching resistor, greatly simplifying design compared to other standards. Only when each endpoint works at different power supply voltages, external coupling components are required.

Table 1 lists the main characteristics of LVDS compared to ECL, PECL, and CML systems. According to the EIA/644LVDS and IEEE1596.3 standards, LVDS uses differential signals with a signal range of 250mV to 400mV and a DC bias of 1.2V.

Table 1 LVDS, ECL, PECL, CML logic standards comparison table

The differential characteristics of LVDS give it many advantages, such as suppressing common-mode noise and generating no noise by itself (assuming that the differential signal is completely synchronized and there is no distortion between the positive and negative outputs). In addition, LVDS can be implemented using CMOS technology and is easy to integrate with other circuits.

Since LVDS is a differential signal, the peak value of the power supply current drawn is low, and the power supply decoupling problem can be solved by adding appropriate decoupling capacitors. Typically LVDS has lower power than ECL and CML, but of course this depends to some extent on the matching scheme used.

2 Applications of LVDS

LVDS is mostly used for clock distribution and point-to-multipoint signal distribution. Clock distribution is very important for digital systems where different subsystems require the same reference clock source, because in most cases the DSP of the base station needs to be synchronized with the RF signal processor, so a phase-locked loop (PLL) needs to be used to generate the required local oscillator frequency. The A/D conversion should also be locked to the center reference clock. When working with wireless receivers, the clock must also be distributed with the lowest possible emissions to avoid impact on small signal paths.

Different strategies can be used to distribute high-speed signals to different units. There are two extreme cases: one is to distribute signals from one signal source/driver to all units (called "multi-point distributor"); the other is is the distribution of multiple signals to a single unit (called a "multipoint to single point multiplexer"). Figure 1 gives the difference between these two situations. For multi-point distributors, the driver must be sufficient to drive all receivers and transmission media (cables, connectors, backplanes), and the bus usually requires matching impedance at the final receiver. The distance between all branches and the bus should be as short as possible to avoid affecting signal integrity. This is not easy with today's high-density circuit boards.

Multi-channel drivers are required in the multi-point to single-point multiplexing structure, which can be regarded as point-to-point operation, which is equivalent to the communication between the driver and a local terminal receiver. This structure reduces signal integrity issues, ensures that the impedance of the transmission medium is as consistent as possible, and eliminates interference caused by multiple branches. The MAX9150 is one such monolithic IC that enables low-jitter, 10-port LVDS trunking from multipoint to single-point multiplexing.

3 Features of MAX9150

The MAX9150 is suitable for high-speed data or clock distribution systems and features low power, low noise, and small size. The chip uses a single LVDS input and can copy a single input to any of the 10 output ports. Figure 2 is its application connection diagram.

The MAX9150 can accept differential signals with an amplitude of 100mV ~ 1V, and the output stage uses a current control circuit to provide an output current of 5mA ~ 9mA. Since the MAX9150 provides a current output, the resistor connected to the external end determines the swing of the differential signal. It is best to use a 50Ω matching resistor for each differential output to facilitate signal distribution at the transmission point with a 100Ω matching resistor at the endpoint. The peak-to-peak jitter of the device is 120ps (maximum value, including deterministic jitter and random jitter). This value can ensure high reliability of data communication in high-speed interconnect applications that are sensitive to time errors, especially for those Systems with embedded clock information. The high-speed switching capability of the MAX9150 LVDS interrupter ensures channel-to-channel error below 100p at data rates of 400Mbps. The MAX9150 operates from a 3.3V supply and consumes less than 160mA at 400Mbps data rates. The low-power shutdown mode reduces the supply current to 10μA. When the input has insufficient drive capability, an open circuit, or a disconnection, the fail-safe function can set the output high to shut down the device. The key parameters of the MAX9150 are listed in Table 2.

Table 2 Key Features of MAX9150

4 Other types of LVDS circuits

Table 3 lists some of Maxim's other types of LVDS chips that can be used with the MAX9150 or as stand-alone devices. Figure 2 is an example of the following two chips used in conjunction with the MAX9150. In the figure, the MAX9110 converts CMOS levels into LVDS levels to provide input to the MAX9150; at the end of the transmission line, the MAX9111 micro SOT32 receiver converts the LVDS levels into COMS level.

Table 3 Maxim’s LVDS chip

5 Summary

For applications with signal rates higher than ten to hundreds of MHz, it is best to use the LVDS logic standard, as the resulting performance indicators are much higher than those using the TTL logic standard. The differential characteristics of LVDS enable it to have extremely high common-mode noise suppression capabilities and provide lower power loss compared to ECL and CML logic. Chips based on LVDS technology can be widely used in clock/signal distribution systems with high data rates of 400Mbps or even higher than 400Mbps. Maxim's system products have extremely low signal jitter and noise, and their power consumption is also low.