TMS320C3X serial port expansion technology

    Abstract: An extension method of the TMS320C3X DSP serial port is introduced, and the Verilog HDL implementation of the interface circuit is given. This interface circuit has been applied to actual systems by the author. Simulation and practice have proven that this circuit is stable and reliable and has certain application value.

    Keywords: digital signal processor hardware description language interface circuit

TMS320C3X is the third generation digital signal processor produced by TI. Currently, four types, including C30, C31, C32 and VC33, have been launched. It is widely used in various fields due to its high cost performance.

TMS320C3X is a 32-bit floating-point DSP. Its programs, data and peripheral addresses are all mapped in the same storage space. It has rich addressing modes and a large addressing space, so access to peripherals is very flexible and convenient. However, in practical applications, some unfavorable factors must also be considered: First, the external bus speed is high and the address line width is high, so the timing requirements for adding external interface circuits are higher, and the circuit connections are more complex; second, frequent peripheral access operations It is easy to cause pipeline conflicts and affect the overall performance. The serial port of DSP has strong device management capabilities and is easy to connect to peripherals, so it has become the first choice for DSP to exchange data with low-speed peripherals. However, in the TMS320C3X series, except that TMS320C30 provides two serial ports, several other chips have only one serial port, which limits the further use of these chips in many cases. This article designs a serial port expansion method based on the characteristics of the C3X serial port, taking the connection between TMS320C3X and TLC3204X as an example.

1 Introduction to the connection between TMS320C3X and TLC3204X

TLC3204X is an analog-to-digital interface chip (AIC) produced by TI. It can be directly connected to the serial port of various DSP chips such as TMS320C3X. Its A/D and D/A conversion accuracy is 14bit and is transmitted in 16bit mode. Two of them are used For chip control and startup auxiliary communication [1]. Figure 1 is the connection diagram of the TLC3204X and TMS320C3X serial ports [2]. AIC and DSP exchange data through DX and DR. AIC's main clock signal (MCLK) is provided by DSP's timer 0, and AIC's shift pulse (SCLK) serves as the serial port's transmit clock (CLKX) and receive clock (CLKR). The transmitting and receiving frame synchronization signals are provided by AIC's FSX and FSR respectively. The DSP serial port works in 16-bit variable speed transmission mode, and the AIC transmits data in word mode.

2 TMS320C3X serial port expansion principle

Generally speaking, the peripheral data word length is shorter, while the TMS320C3X serial port data word length can be flexibly configured. Taking advantage of this feature, the interface can be expanded on the existing basis by adding a small amount of external circuits. In this example, the TLC3204X data is 16-bit word length, so as long as the TMS320C3X serial port is set to 32-bit transmission mode, and each TLC3204X point uses 16 bits, the serial port can be divided into two. Figure 2 is a schematic diagram of the connection between TMS320C3X and two TLC3204X. The design of the interface circuit can be divided into two parts: sending and receiving.

2.1 Transmitting interface circuit

This interface should accomplish two tasks. The first is to receive 32-bit data from the TMS320C3X serial port. The TMS320C3X provides the shift pulse CLKX. The frame synchronization signal (FSX) is provided by the interface circuit. Its timing is shown in Figure 3. The second is to decode the 32-bit data into two 16-bit data, and then transfer it to two TLC3204X chips. The TLC3204X chip provides the transmission clock SCLK, frame synchronization signal FSX, and completion signal EODX. The transmission timing is shown in Figure 4.

2.2 Receiving interface circuit

This interface circuit is the reverse process of the sending interface circuit, and its timing is shown in Figure 5 and Figure 6.

3 Implementation of interface circuit

Verilog HDL[3] describes the structure of hardware units in a simple and easy-to-read manner. It is one of the two most popular and common hardware description languages ​​currently and is supported by many EDA tools. Therefore, using this language for circuit design can save development costs and shorten the time. Development cycle.

3.1 Top-level Verilog HDL description of the interface circuit

module DSP_TLC(SCLK1,DX1,FSX1,EODX1,DR1,FSR1,

EODR1,SCLK0,DX0,FSX0,EODX0,DR0,FSR0,EODR0,

CLKX,DX,FSX,DR,FSR,RESET);

input FSX1,EODX1,FSX0,EODX0,DX,CLKX,RESET;

output FSX,DX1,EX0;

input DR1,SCLK1,FSR1,EODR1,DR0,SCLK0,FSR0, EODR0;

output FSR,DR;

Transmit TRA(DX1,SCLK1,FSX1,EODX1,DX0,SCLK0,

FSX0,EODX0,DX,CLKX,FSX,RESET);

Receive REC(DR1,SCLK1,FSR1,EODR1,DR0,SCLK0,

FSR0,EODR0,DR,CLKX,FSR,FESET);

Endmodule

3.2 Verilog HDL description of transmit interface circuit

module Transmit(DX1, SCLK1,FSX1,EODX1,DX0,

SCLK0,FSX0,EODX0,DX,CLKX,FSX,RESET);

input SCLK1,FSX1,EODX1,SCLK0,FSX0,EODX0;

input DX,CLKX,RESET;

output FSX,DX1,DX0;

reg [31:0] tmp_DX,temp_DX;

reg [1:0] tmp_EODX;

reg [4:0] DX_count;

assign DX1=temp_DX[31];

assign DX0=temp_DX[15];

assign FSX=(tmp_EODX = =2'b11)? 1'b0:1'b1;

always @(negedeg CLKX or negedge RESET)

begin

if (RESET= =1'b0)

begin

tmp_DX <=32'b0;

tmp_EODX <=2'b0;

DX_count <=5'b0;

end

else

begin

if (EODX1 = =1'60)tmp_EODX[1] <=1'b1;

if (EODX0 = = 1'b0)tmp_EODX[0] <=1'b1;

if (DX_count = =5'b11111)tmp_EODX <=2'b0;

if (FSX = =1'b0)

begin

tmp_DX[0] <=DX;

tmp_DX[31:1] <=tmp_DX[30:0];

DX_count <=DX_count +1;

end

else

DX_count <=5'b0;

end

end

always @(posedge SCLK1)

begin

if (FSX1 = =1'b0)

temp_DX[31:17] <=temp_DX[30:16];

else

temp_DX[31:16] <=tmp_DX[31:16];

end

always @(posedge SCLK0)

begin

if (FSX0 = =1'b0)

temp_DX[15:1] <=temp_DX[14:0];

else

temp_DX[15:0] <=tmp_DX[15:0];

end

endmodeule

3.3 Verilog HDL description of receiving interface circuit

module Receive(DR1,SCLK1,FSR1,EODR1,DR0,SCLK0,FSR0,EODR0,DR,CLKR,FSR,RESET);

input DR1,SCLK1,FSR1,EODR1,DR0,SCLK0,FSR0,EODR0;

input CLKR,RESET;

output FSR,DR;

reg [31:0] tmp_DR,temp_DR;

reg [1:0] tmp_EODR;

reg [4:0] DR_count;

assign DR=(FSR = =1'b0) ? tmp_DR[31]:1'bz;

assign FSR=(tmp_EODR = =2'b11)?1'b0:1'b1;

always @(posedge CLKR or negedge RESET)

begin

if (RESET = =1'b0)

begin

tmp_DR <=32'b0;

tmp_EODR <=2'b0;

DR_count <=5'b0;

end

else

begin

if (EODR1= =1'b0) tmp_EODR[1] <=1'b1;

if (DR_count = =5'b11111) tmp_EODR <=2'b0;

if (FSR = =1'b0)

begin

tmp_DR[31:1] <= tmp_DR[30:0];

DR_count <=DR_count +1;

end

else

begin

DR_count <=5'b0;

tmp_DR <= temp_DR;

end

end

end

always @(negedge SCLK1)

begin

if (FSR1= =1'b0)

begin

temp_DR[16] <=DR1;

temp_DR[31:17] <=temp_DR[30:16];

end

end

always @(negedge SCLK0)

begin

if (FSR0 = 1'b0)

begin

temp_DR[0] <=DR0;

temp_DR[15:1] <= temp_DR[14:0];

end

end

endmodule