Application of isp1032E in high-precision data acquisition system

introduction

ISP in-system programmable technology is different from the previous PLD which requires a dedicated burner to realize logic design. It does not need to remove the ISP device to realize the repeated design and programming of the required circuit logic design. This greatly facilitates system design and development, circuit board debugging and upgrade maintenance, thereby shortening the system development cycle and realizing the software design of hardware circuits.

Compared with commonly used PLD devices, ISP devices have the advantages of small size, large capacity, easy programming, and easy online debugging. They can realize large-scale circuit design and can realize programming encryption. Especially when there are many input and output pins, it can greatly optimize system design and save system space. Compared with FPGA devices, the capacity of ISP devices is smaller, but once the logic in the chip is loaded, it will not be lost due to power failure. If you want to change the logic, you only need to reload it through the download cable, without the need for off-chip expansion EPROM to store the structural data of the circuit, so the circuit implementation is more convenient and simple. In fact, for circuit designs that do not generally have overly complex logical calculations, its capacity is generally sufficient. The following is

Taking Lattice's isp1032E as an example, this paper introduces the application technology of isp devices in high-precision data acquisition systems.

2 isp1032E device introduction

2.1 Internal structure and timing model of isp1032E

The internal structure of isp1032E is shown in Figure 1. The device has 6000 gate unit logic, 192 register units, 64 general I/O, 8 dedicated input pins, 4 dedicated clock inputs, and a centralized connection pool GRP that can provide internal interconnection of the above parts. The basic logic unit of isp1032E is the universal logic block GLB, which has 32 in total and is labeled A0 to D7. Each GLB unit corresponds to 18 input units, 1 AND/NOR logic array, and 4 output units. The input units of GLB come from GRP and dedicated inputs; all output units need to enter GRP to facilitate connection to other input units.

The internal timing model of isp1032E is shown in Figure 2. GOE0 and GOE1 are the output enable pins of all I/O units. This pin can also be used as a dedicated input pin. The external dedicated clock input pin Y0 is connected to a clock input pin of all GLB units; Y1 can be selected to control the clock input of any GLB unit after entering the clock distribution network; Y2 can be selected to be connected to any GLB unit or I/O unit after entering the clock distribution network; Y3 can be selected to be connected to any I/O unit after entering the clock distribution network. The RESET key can be used to reset all GLB units or I/O register units.

Figure 1

Figure 2

2.2 Hardware Implementation of System Logic Loading

When loading system logic through hardware, first use Lattice's dedicated compiler software ispDesignExpert to generate the required JED fuse map file, and then use is-pDCD (ispDaisyChainDownload) in the dedicated download software ispVMSystem to convert the JED fuse map file into the form of an isp stream, so that the logic to be generated can be burned into the corresponding isp device through the download cable using the PC parallel port.

Figure 3

The programming interface protocol of the ISP device download cable adopts the Lattice ISP protocol or the ispJTAG protocol standard. The ispLSI1000/E and 2000 series, as well as the ispGDS and ispGAL series can only be programmed through the Lattice ISP interface; the ispLSI2000V series can only be programmed using the ispJTAG standard; the remaining ispGDX, ispLSI3000 and 6000 series can use both of the above protocols.

The schematic diagram of the above process through the download cable is shown in Figure 3. It should be noted that a 0.01μF filter capacitor must be added between the ispEN signal and the ground in the figure, and the closer the capacitor is to the ISPEN pin, the better. This is because during the download process, the is-pEN signal is low-level valid, so it is easy to be interfered and drown out the weak valid signal.

3 Software Process

The software design process of the data acquisition system is shown in Figure 4. Usually, when designing software, the graphical input method and the hardware language description method have their own advantages. The graphical input method is relatively simple and clear, and is easy to debug; while the hardware description language has a greater advantage in writing complex circuit designs. In fact, the hybrid input method has the advantages of both methods above, and therefore has a wide range of applications. [page]

4 Application in data collection

Figure 4

4.1 Project Background

A common feature of modern test systems is high-speed, high-precision and multi-parameter comprehensive testing. In the backplane engine parameter comprehensive test system, the conditioned output of strain, piezoresistance, thermal resistance sensors and thermocouple signals need to be collected and processed with high precision. In order to achieve high-precision performance indicators and give full play to the advantages of DSP's fast speed and powerful computing functions, the author designed a high-precision data acquisition board consisting of a processor with DSP as the core, a control unit with ISP decoding control circuit as the core, a multi-channel analog switch selection circuit, a program-controlled amplifier circuit and a program-controlled analog filter circuit, a high-precision ADC analog-to-digital conversion circuit, and a DAC zeroing and self-calibration circuit. The test system can achieve high-precision data acquisition internally, and can communicate data with other instrument boards or interconnected devices through the instrument bus through ISP decoding control externally.

4.2 Overall structure of the system

FIG5 is the overall structure of the high-precision data acquisition system.

The ADC in the system uses CRYSTAL's 24-bit serial dual-channel output analog-to-digital converter CS5397 to achieve high-precision data acquisition. In order to detect the function of the analog channel, the channel input signal can be switched to the internal DAC zero adjustment and self-calibration circuit, so that the DAC zero adjustment and self-calibration circuit can generate specific DC and AC signals as calibration signals. This calibration signal can be used to calibrate the gain and zero offset of the channel and improve the system accuracy. In order to achieve the ideal amplitude-frequency characteristics, the system adopts a working mode combining front-end analog filtering and back-end DSP digital filtering.

4.3 Application Results

The ISP decoding control circuit (schematic diagram) of the DAC zeroing and self-calibration circuit is shown in Figure 6. After the program is successfully burned into the ISP chip, the DAC (DAC7614) serial input data and input clock can be controlled by ISP address decoding to turn on or off, and the required analog voltage value for zeroing and self-calibration can be output according to the working characteristics of the DAC.

Figure 5

Figure 6

In circuit design, due to the large number of latches used, it may cause insufficient system resources (insufficient number of latches), so the system is specially designed with a D flip-flop circuit to solve the problem of insufficient D flip-flop resources. Its schematic diagram is shown in Figure 7.

5 Summary

ISP in-system programmable technology and its corresponding device ISPLSI were first created by Lattice in 1992. Its advanced ideas and flexible in-system programmable methods have greatly impacted traditional digital circuit design, thus bringing a technological revolution to digital circuit design.

In November 1999, Lattice launched ispPAC (In-System Programmability Programmable Analog Circuits), which opened a new chapter in the development and research of analog circuits. Although Lattice's development tools are slightly inferior to those of ALTERA and XILINX, the company is very distinctive in the development of small and medium-sized PLDs. Especially after acquiring Vantis (formerly a subsidiary of AMD) in 1999, Lattice has become the world's third largest supplier of programmable logic devices.