Design of hierarchical distributed management system based on DSP chip

　　1 Overview

　　1.1 Background

　　Digital signal processors (DSPs) are generally used to run core data processing algorithms, but in some special environments, DSPs must be used to manage the core chips of the control unit. This article presents a hierarchical distributed image processing system, in which the core chip of the management computer is AD's floating-point DSP (ADSP21020). It not only undertakes the management and control tasks of the image processing system, but also must respond in real time to execute key instructions from the superior 1553 bus. This article focuses on the coordinated control of two-level distributed systems based on DSP chip management computers.

　　1.2 System introduction

　　This image processing system is a distributed computer system consisting of 5 modules, including a pre-processing unit, mass memory, offline data parallel processing unit, communication unit and management computer. The management computer is the control core of this system. It manages the internal system through the RS485 bus and communicates with the superior system through the 1553 bus.

　　The internal control function of the management computer is divided into two categories: real-time control and non-real-time control. Real-time control is for tasks with strict timing requirements and real-time response. The management computer provides control pulses to the CCD detector and communication unit through the exclusive RS422 serial bus. Non-real-time control is aimed at signals that do not require time accuracy and can even be interrupted by other programs, that is, the serial bus RS485 that transmits instructions and data. As the management computer at the control core, it exchanges data with other units and queries the health status.

　　The key to the design of the management computer lies in the coordination between the two-level distributed systems, including the parallel management of the RS485 bus and the 1553 bus, and the switching of the two working modes of accepting external control and managing internal units. The two-level distributed system is shown in Figure 1. This article mainly discusses this part.

　　2 Design of management computer

　　2.1 Analysis of the work of the management computer The management computer has two working modes: ① receiving 1553 bus instructions and data; ② managing and controlling the internal units of the image processing system. The information sent by the 1553 bus mainly includes processing task type, working time, number of working times, status detection, etc. The internal management tasks of the management computer include the transmission of relevant image public information, such as the time and location of image generation, and health status detection.

　　The management computer's priority in receiving 1553 bus instructions and data is obviously higher than the internal management work. Under normal circumstances, the management computer is always in the state of internal management, so when a command is sent from the 1553 bus, it must interrupt its internal management work, save the working state, and respond to the command of the upper 1553 bus.

　　The 1553 bus interrupt management computer can work in two different ways: precise interrupts and imprecise interrupts. Precise interruption means that no matter what work the management computer is doing, it must be stopped immediately. Inexact interrupt means that you must wait for the management computer to complete the communication task before responding to the 1553 bus interrupt. Considering that the commands sent by the 1553 bus do not have very demanding time requirements, and considering the complexity of the design, the second strategy, namely imprecise interruption, is adopted in the image processing system.

　　Since the design uses imprecise interrupts, commands sent from the 1553 bus cannot be responded to in a timely manner, and a buffering strategy must be used. A FIFO dual-port memory with first-in-first-out function is used here. It can automatically receive and temporarily store data from the 1553 bus, and the management computer also sends data to the 1553 bus through FIFO. The functional block diagram of the management computer unit is shown in Figure 2.

　　2.2 1553 bus interface design

　　The interface between the 1553 bus RT board and the management computer is realized through a shared dual-port FIFO buffer memory. The FIFO uses CY7C439 bidirectional memory. The 1553 bus interface design is shown in Figure 3.

　　2.3 RS485 interface design

　　The RS485 interface is implemented by the parallel-to-serial conversion chip TL16C550 and the RS485 driver receiver MAX489, as shown in Figure 4.

　　2.4 Coordination of 1553 bus and RS485 bus

　　The program for managing the computer includes three parts: 1553 bus communication program, RS485 communication program and RS485 status saving program. Their communication method is through interrupts. The 1553 bus communication program is implemented through the FIFO interrupt method, while the RS485 bus communication program responds to the TL16C550 interrupt. The DSP has four user interrupt lines. Since the priority of the 1553 bus interrupt is greater than that of the RS485 bus, the interrupt vector 1553 bus is set to a higher priority part inside the DSP.

　　The program control flow is shown in Figure 5.

　　3 Principle prototype debugging results

　　3.1 RS485 bus debugging

　　The RS485 bus communication protocol adopts NRM (normal response mode). Other units in the system cannot directly send information to the management computer. The management computer must send commands and they respond to the commands. Communication between each controlled unit must be carried out through the management computer. The corresponding data transmission includes image time, image area, working status of the instrument (temperature, pressure, etc.), and working mode. The format of the data frame is as follows: Flag 7-bit address 7-bit control 7-bit information frame check flag 7-bit control word: command, data identification. Test results: ① All types of data are received correctly; ② The recipient can start the self-test program and return corresponding information.

　　3.2 1553 bus interface debugging

　　The FIFO interrupt line is connected to the highest priority INTR0 of the DSP. The management computer serves as the RT of the 1553 bus and interprets and executes the 1553 standard frame format instructions. Test results: ① When the management computer is idle, it can respond to the 1553 bus interrupt in time; ② When the management computer sends information to RS485, it can respond correctly to the 1553 bus interrupt; ③ When the management computer receives RS485 information, the sender cannot know the interrupt status , and still continue to send. The solution is that after returning from the interrupt, the management computer sends an instruction requesting retransmission to the device.

　　Conclusion

　　This article discusses the design of a DSP-based management system, focusing on the coordination between two levels of distributed systems. On the 1553 bus interrupt, if precise interrupts are used, the program will be very complicated, but it will be of great benefit to the real-time control system. Since the real-time nature of high-level commands in this system is not very strong, it is enough to use non-precise interrupts.