Design of FIR filter for DA algorithm

1. Introduction
In digital signal processing systems, FIR digital filters mostly use dedicated DSP chips (such as TMS320CXX series). This DSP-based processing system has many advantages, such as flexible solutions, strong operability, and easy program portability. However, filters of this structure are mostly written based on the data shift, multiplication and accumulation algorithm of the FIR filter, and the filter design is completed by combining software and hardware. Since the instructions are executed serially when the software is running, this seriously restricts the operating rate of the system and cannot meet the real-time processing requirements of digital signals with high transmission rates and large data throughput. The FPGA filter based on the DA algorithm is a way to implement the FIR filter in a pure hardware way. The outstanding advantage of this method is the fast operation speed, which is particularly suitable for high-speed, real-time, and fast-changing digital signal processing requirements.

2. Basic idea of ​​DA algorithm
The first discussion of distributed arithmetic (DA) can be traced back to a paper by Cr0i Croisier in 1973, which was promoted by Peled and Liu. However, it was not until the emergence of FPGA that it was widely used in FPG to calculate product sums. In FPGA chip design, distributed arithmetic (DA) is a very important technology. It has been widely used in product sum calculations. In order to understand the design principle of DA algorithm, we consider that the output of a linear time-invariant network can be expressed as follows: Assume that the coefficient c[n] is a known constant and x[n] is a variable. In the signed DA system, assume that the expression of the variable x[n] is as follows: Where xb[n] represents the bth bit of x[n], that is, x[n] is the nth sample point of x. Therefore, the inner product y can be expressed as: We re-sum the order separately (this is the origin of the distributed algorithm), and the result is: y=(c[0]x _B-1 [0]+c[1]+……+c[N-1]x _B-1 [N-1])2 ^B-1 +(c[0]x _B-2 [0]+c[1]+……+c[N-1]x _B-2 [N-1])2 ^B-2 (2-4) . . . +(c[0]x ₀ [0]+c[1]x ₀ [1]+c[N-1]x ₀ [N-1])2 ⁰ It can be expressed in a more compact form as follows: From formula (2-4), it can be found that the distributed algorithm is a method of operation for the purpose of realizing multiplication and addition operations. The difference between it and the traditional algorithm for realizing multiplication and addition operations is that the order of executing partial product operations is different. When implementing the multiplication and addition function, the distributed algorithm adds the partial products generated by each corresponding bit of each input data in advance to form the corresponding partial products, and then adds the partial products to obtain the final result. The traditional algorithm waits until all the products have been generated before adding them to complete the multiplication and addition operation. Compared with the traditional serial algorithm, the distributed algorithm can greatly reduce the scale of the hardware circuit and improve the execution speed of the circuit.

3. Hardware implementation of FIR digital filter based on DA algorithm
From the above analysis, we can know that any linear time-invariant network can always be converted into the form of formula (2-5). FIR filter is a very typical linear time-invariant network. Its expression is: We can convert it into the following form: In this system, 8-bit input is used, so B = 8 Then: The linear phase FIR filter satisfies the coefficient symmetry condition. The system designed in this system is 16-order, so its coefficient is even symmetric about h[7], that is: h[n]= h[16-1-n]= h[15-n] (3-4) From formulas (3-3) and (3-4), the hardware block diagram of the implementation system can be obtained as shown in Figure 3-1:

4. VHDL description of the system
4.1 Top-level module design
Library ieee;
Use ieee.std_logic_1164.a11;
Use ieee.std_logic_unsigned.all;
Entity FIR is
Port (x: in std_logic_vector(7 downto 0);
clk : in std_logic;
y : out std_logic_vector(7 downto 0));
end FIR;
architecture behave of FIR is
component lpfir
port (
in : in std_logic_vector(7 downto 0);
clk : in std_logic;
out : out std_logic_vector(7 downto 0));
end component ;
begin
process(clk)
begin
u1：lpfir port map (x,clk,y);
end process;
end behave;

4.2 Establishment of LUT lookup table ROM
ROM initialization value edited in MIF file format
WIDTH = 16
DEPTH = 16
ADDRESS_RADIX = HEX ;
DATA_RADIX = HEX ;
CONTENT BEGIN
0 : 0000;
1 : 0045;
2 : 00E6;
……
F : 0000;
END;

4.3 Design of filter coefficients
We use the filter design tool FDAtool and signal processing tool Pstool of matlab to design a 16-order window function FIR low-pass filter. Its specific parameters are:
window function type: Blackman window, signal sampling frequency: 50KHz, passband cutoff frequency 10KHz, filter coefficient h[n] see Table 1 below, the transmission characteristics of the filter are shown in Figure 4-1 below:

5. System simulation and result analysis
In order to verify and test the effect of the system, we used Cyclone's EP1C6Q240C8 chip to develop the system, and used ALTERA's comprehensive design tool Quartus II 4.2 to compile and simulate the system. We continuously input 16 data (0.3, 0.32, -0.79, 0.45, -0.87, -0.91, -0.12, 0.89, 0.37, 0.66, -0.57, 0.75, -0.21, 0.96, 0.56, -0.19) to process the system and obtained the following simulation results. 5.1 Simulation results of system comprehensive performance The comprehensive performance of the system is shown in Table 5-1: It can be seen from Table 5-1 that the system occupies very few hardware resources and runs at a very high speed. 5.2 Simulation results of system processing accuracy The system processing results are compared with the theoretical results in Table 5-2: In order to obtain a more accurate result, the last 8 data are taken for analysis. From Table 5-2, we can see that the actual processing results of the system have a small error with the theoretical calculation results, which can meet the needs of actual engineering.

6. Conclusion The
above theoretical analysis and simulation results show that compared with the DSP algorithm that combines software and hardware and executes serially, the DA algorithm has the obvious advantages of low system resource occupation and high operating speed, and is a more effective FIR filter design method; the digital signal processing design based on the DA algorithm has incomparable advantages over the DSP algorithm. While greatly improving the processing speed and data throughput of the FIR digital filter, it can also ensure that the system has very small processing errors. It is a relatively practical, reliable and efficient design method.