Avalon bus PWM design in NiosⅡ system

In the process of building the NiosⅡ system, the SoPC Builder development environment integrates many commonly used types of device models for developers to call. In the ever-changing embedded system design, the interface devices integrated in the development environment are very limited and sometimes cannot meet the needs of developers. The SoPC Builder development tool allows users to expand their required devices according to the rules to complete the design and development of the system. Developers integrate device drivers into the hardware abstraction layer (HAL) of SoPC Builder according to the Avalon bus specification and load and use them in the SoPC Builder environment, which facilitates users to develop a customized system on chip. This article introduces the process of customizing Avalon devices by integrating the pulse width modulation (PWM) slave peripheral based on the Avalon bus inside the NiosⅡ embedded system. It is applied to the embedded intelligent car monitoring system and provides some methods and suggestions for developers using the Nios II processor.

1 Introduction to Customized User Peripherals Based on Avalon Bus

The Avalon bus of NiosⅡ is different from the fixed peripherals of other microprocessors. The peripherals of NiosⅡ can be customized arbitrarily, which allows users to customize according to specific application requirements. All NiosⅡ system peripherals are connected to the NiosⅡ soft core through the Avalon bus to exchange data. Therefore, user-defined peripherals must comply with the bus protocol to establish a connection with NiosⅡ.

The Avalon signal interface defines a set of signal types such as chip select, read enable, write enable, address, data, etc., which are used to describe the address-based read and write interface on the master and slave peripherals. The peripherals use accurate signals to interface with their core logic and remove signals that add unnecessary overhead.

In the Nios Ⅱ system, a custom device consists of the following parts:

(1) Hardware file: A hardware description file written in HDL language that describes the logic of custom device components.

(2) Software files: device register files and device driver files written in C language.

(3) Device Description File (Ptf): This file describes the structure of the device and contains the information required for SoPC Builder to configure and integrate it into the system. This file is automatically generated by SoPC Builder based on the hardware files and software files.

2 PWM Design Based on NiosⅡ System

PWM is a very effective technology for controlling analog circuits using digital outputs. It is widely used in many fields from measurement and communication to power control and conversion. In fact, PWM is a method of digitally encoding the level of analog signals. Through the use of high-resolution counters, the duty cycle of a square wave is modulated to encode the level of a specific analog signal. The PWM signal is still digital because at any given moment, the full-amplitude DC power supply is either completely present or completely absent. The voltage or current source is applied to the analog load in a repetitive sequence of pulses that are on or off. On means that the DC power supply is applied to the load, and off means that the power supply is disconnected. As long as the bandwidth is sufficient, any analog value can be encoded using PWM.

2.1 Hardware Design

Hardware files refer to HDL files, which consist of the following modules:

Logic module: describes the logical function of the device;

Register mapping module: provides a communication interface between the internal logic module and the Avalon bus;

Avalon bus interface module: enables the Avalon bus to access registers to complete corresponding logical functions.

2.1.1 Logical Structure

The custom PWM is also composed of the above modules. PWM is designed according to the following requirements:

(1) The task logic operates synchronously with a simple clock.
(2) The task logic uses a 32-bit counter to provide a certain range of period and duty cycle for PWM. The maximum period can be set to 232 clks.
(3) A microcontroller can be used to set the period and duty cycle values ​​of PWM, so an interface and control logic that can read and write registers is required.
(4) Registers are defined to store the values ​​of PWM period and duty cycle.
(5) The microcontroller can turn off the PWM output by controlling the disable bit of the register.

The structure diagram of PWM task logic is shown in Figure 1.

The PWM task logic consists of an input clock (clock), an output signal port (pwm_out), an enable bit, a 32-bit counter, and a 32-bit comparison circuit. clk is the clock signal of the 32-bit counter. The 32-way comparison circuit compares the current value of the 32-bit counter with the value in the duty cycle setting register (Duty Cycle Value Register) to determine whether the output of pwm_out is high or low. When the value in the current counter is less than or equal to the value in the duty cycle register, pwm_out outputs a low level, otherwise it outputs a high level. The PWM cycle setting register (Modulo_n ValueRegister) is used to set the signal cycle of pwm_out. When the current counter value is equal to the setting in the cycle setting register, a reset signal is generated to clear the value in the counter. The enable control register (EnableControl Register) can make the clock signal valid or invalid, that is, control whether the counter counts, thereby keeping the pwm_out output unchanged at the current level.

The PWM internal includes the Enable Control Register, the Modulo_n Value Register, and the Duty Cycle Value Register, as shown in Figure 1. In the design, each register is mapped to a separate offset address in the Avalon slave port address space. Each register can be read/written, and the software can read back the current value in the register. Table 1 is a list of PWM registers and offset addresses.

The Avalon interface of PWM requires a simple slave port, which uses Avalon bus signals to complete register read/write transfers. The signals required for PWM and Avalon bus interface are shown in Table 2.

2.1.2 Hardware Design Files and Simulation

The PWM hardware design file contains three HDL files written in Verilog as shown in Table 3.

pwm_tasK_logic.v completes the logic function of PWM. Figure 2 is the simulation waveform of this file in QuartusⅡ environment.

In Figure 2: the clock_divide signal sets the number of clocks in the PWM output cycle, and the dutv_cycle signal sets the number of clocks in which the PWM outputs a low level within a cycle. The two signal setting values ​​determine the duty cycle and period of the PWM signal.

2.2 Software Design

If you want the Nios soft core to be able to access custom devices, you must write device drivers based on the previous hardware design and the file structure of the hardware abstraction layer. Take PWM as an example to illustrate the file structure of HAL, as shown in Table 4.

2.3 Encapsulating PWM Design as SoPC Builder Component

When the hardware files and software files have been established, you can use the device editor in SoPC Builder to encapsulate the custom device into the development environment, and call it directly when building the NiosⅡ system. Click Create New Component in SoPC Builder, create a new component wizard to add HDL files, set signals and interfaces to add software, and finally generate a folder containing description files, folders for users to store hardware description files, and HAL folders for containing HAL software files.

2.4 Building the Nios System

The built kernel file is compiled in QuartusⅡ to generate a pof configuration file and download it to the E2PROM chip. Then you can use the Nios IDE development environment to edit the user program and debug the application on the target board through JTAGBlaster or USB Blaster.

3 Application of Customized Peripheral PWM in Embedded Intelligent Car Monitoring System

The design of the intelligent car monitoring system uses the SmartSoPC core board of Zhou Ligong Company, the FPGA is Altera's EPlC12, and the NiosⅡ processor is used as the embedded CPU. The robot car has two motors, the left wheel motor and the right wheel motor. This part includes the motor drive circuit and the motor control circuit, that is, the drive and control of the left motor and the drive and control of the right motor. The drive circuit uses the high-power DC motor drive chip L289 of CTMicroelectronics. The speed control uses PWM to control the forward speed of the car. The control word is written by the FPGA to obtain PWM drive signals with different duty cycles. This PWM signal is sent to the control end of the motor drive chip to adjust the speed. Call the motor driver program, change the PWM duty cycle, output PWM waves, and realize the speed control of the motor. When the PWM signal is used to control the speed of the DC motor, the motor will not run stably when the frequency is low, and the driving efficiency of the PWM signal is reduced when the frequency is high. After multiple tests of the actual circuit, the debugging results show that the effect is better when the frequency is between 500 and 1,000 Hz. Some C language control codes are as follows:

4 Conclusion

The NiosⅡ embedded processor is a user-configurable general-purpose RISC embedded processor, which is a very flexible and powerful processor. Embedded system design based on this technology can easily integrate general equipment and custom equipment modules into the system, enriching the interface resources, so that users can quickly develop a customized system-on-chip, improve efficiency, and shorten the development cycle. This article uses the method of customizing PWM peripherals and proves the feasibility and correctness of the solution through hardware testing, hoping to provide some methods and suggestions for developers using NiosⅡ processors.