FPGA Application of Audio Codec Chip Interface

This paper introduces the design of the FPGA-based interface circuit of the audio codec chip WM8731 , including the chip configuration module and the audio data interface module, so that the controller can easily operate it only through registers. The whole design is implemented in Max+Plus Ⅱ with VHDL and Verilog HDL languages ​​and verified.

1 Overview

WM8731 is a powerful low-power stereo 24-bit audio codec chip. Its high-performance headphone driver, low-power design, controllable sampling frequency, and selectable filter make WM8731 chip widely used in portable MP3, CD, and PDA. Its structural block diagram is shown in Figure 1.

WM8731 includes 2 line inputs and 1 microphone input with volume adjustment; built-in on-chip ADC (analog-to-digital converter) and selectable high-pass digital filter; DAC (digital-to-analog converter) with high-quality oversampling rate structure; line output and headphone output; built-in crystal oscillator and configurable digital audio interface and 2 or 3-wire optional microprocessor control interface. The controller can configure WM8731 through the control interface (Control Interface), and then read and write data audio signals through the digital audio interface (Digital Audio Interface). This paper designs a driver module based on FPGA, which converts the control interface and digital audio interface of WM8731 into a common bus interface of the controller, so that the controller can control and use the WM8731 chip like reading and writing external registers.

2 Introduction to WM8731 chip interface timing

2.1 Control interface timing

The control interface of WM8731 has 4 pins, namely: MODE (control interface selection line), CSB (chip select or address selection line), SDIN (data input line) and SCLK (clock input line). It has two modes: 2-wire and 3-wire. 2-wire is MPU interface, 3-wire is compatible with SPI interface. The configuration selection of the control interface can be completed by setting the state of the MODE pin. When MODE is selected as 0, it is 2-wire mode, and when it is 1, it is 3-wire mode. This article uses 2-wire mode to control WM8731. Its timing diagram is shown in Figure 2.

2.2 Digital Audio Interface Timing

The digital audio interface of WM8731 has 5 pins, namely: BCLK (digital audio bit clock), DACDAT (DAC digital audio data input), DACIRC (DAC sampling left/right channel signal), ADC-DAT (ADC digital audio signal output), ADCLRC (ADC sampling left/right channel signal).

The digital audio interface can work in master mode and slave mode. The 6th bit of the register with address 0000111 sets the master/slave mode of the data: "1" is master mode, "0" is slave mode. ADCDAT, /DACDAI and ADCLRC/DACLRC are synchronized with the bit clock BCIK and are transferred once on each falling edge of BCLK. BCLK and ADCLRC/DACLRC are output signals in master mode and input signals in slave mode. DAC-DAT is always an input signal and ADCDAT is always an output signal.

Digital output supports 4 audio data modes: right-aligned, left-aligned, I2S and DSP mode. The data format of the transmission can be set by configuring the registers differently. The register configuration values ​​are as follows:

Bits 1 to 0 of register address 0000111 set the audio format: "11" is DSF' format, "10" is I2S format, "01" is left-aligned format, and "00" is right-aligned format.

3-2 bits set the word length: "11" is 32 bits, "10" is 24 bits, "01" is 20 bits, and "00" is 16 bits.

These four audio formats are all MSB first, 16 to 32 bits, but 32-bit data does not support right-aligned mode.

This article adopts the left-aligned data format of the master mode. The left-aligned data format transmission is shown in Figure 3: In the left-aligned format, the MSB is valid on the first rising edge of BCLK, followed by an ADCLRC or DACLRC transmission.

3 FPGA Design of WM8731 Chip Driver

3.1 Overall design of the driver

The block diagram of the driver designed in this paper is shown in Figure 4. The dual-port RAM and the driver are connected to the data bus and address bus of the controller. The controller only needs to provide a small number of control lines to complete the control and data exchange functions of the audio codec chip wM8731.

The internal structure diagram of the driver is shown in Figure 5. The control part provides the interface between the driver and the controller (including data bus signals, address bus signals and control signals), and generates control signals for the control word conversion unit and the digital audio interface unit; the internal register caches the control word and status word; the control word conversion unit is responsible for sending the control word serially to WM8731 and verifying the transmission signal; the data audio interface unit completes the serial-to-parallel conversion between WM8731 and the external dual-port RAM, realizing the sending and receiving functions of digital audio signals.

drive

Table 1 Corresponding definitions of status register control words

3.2.2 Control word conversion unit

When the START control bit is set to '1', the data in the control word register is sent serially to WM8731. When an error occurs during transmission, the ACK bit in the status register is set to 1. See Figure 6.

3.2.3 Digital Audio Interface Unit

When the read-in digital audio flag C1 is '1', the digital audio data from the WM8731 chip is received and stored in the external dual-port RAM. When the output digital audio data flag C2 is '1', the audio data in the dual-port RAM is sent to the wM8731. See Figure 7.

3.3 System Simulation

The following is the timing simulation of the controller writing the control word to WM8731 through the driver module as shown in Figure 8. The definition of each pin in the figure is shown in Table 2.

4 Conclusion

The interface circuit of the audio codec chip WM8731 is designed using FPGA, which realizes the unified control of the control interface and the digital audio interface, simplifies the use steps of the audio codec chip WM8731, and has the advantages of good scalability, simple and convenient use, and easy upgrade. It also has certain reference significance for the interface design of other chips.