Application of IRIG-B code timing method based on CPLD in relay protection device

Accurate and unified time is the most basic requirement of substation automation system. Only when various automation equipment in the power system (such as fault recorders, relay protection devices, RTU microcomputer monitoring systems, etc.) adopt a unified time base, can the cause and process of the accident be accurately analyzed based on the fault recording data, the sequence and accurate time of the actions of each switch and circuit breaker. Unified and accurate time is an important measure to ensure the safe operation of the power system and improve the operation level. The emergence of the Global Positioning System (GPS) makes it possible to realize these requirements.

There are three kinds of GPS-based time synchronization methods: 1) pulse time synchronization method; 2) serial port time synchronization method; 3) IRIG-B time code time synchronization method. Pulse time synchronization and serial port time synchronization have their own advantages and disadvantages. The former has high accuracy but cannot directly provide time information, while the latter has relatively low time synchronization accuracy. The IRIG-B code time synchronization method takes into account the advantages of both. It is a time synchronization method with high accuracy and absolute accurate time information. When using IRIC-B code time synchronization, there is no need for field bus communication message time synchronization, nor is there a need for GPS to output a large number of pulse node signals. The technical specifications issued by the State Grid Corporation of China clearly require that the newly commissioned substation automation system bay layer equipment that requires time synchronization should, in principle, use the IRIG-B code (DC) method to achieve time synchronization.

1 Timing scheme for relay protection devices

A time synchronization system is configured in a substation, and the time synchronization system can be composed of one or more clock device screens. The structure of the time synchronization system can adopt a master-slave or master-standby structure. The EIA RS-422/485 interface standard is used to transmit IRIG-B (DC) code signals between the time synchronization system and the relay protection device to be timed. Protection devices from different manufacturers only need to have an IRIG-B code decoder with an EIA RS422/485 interface to access the unified time synchronization network of the substation. The protection device is embedded with an IRIG-B code decoding module and adopts the time synchronization mode in Figure 1, that is, the IRIG-B code decoding module detects the time information and the time synchronization pulse, and sends the time information directly to each functional plug-in through the serial port. Each functional plug-in directly imports the time synchronization pulse from the time synchronization module.

2 Hardware Design of IRIG-B Code Decoding Module

Early B-code decoding equipment mostly used a combination of TTL integrated circuits and single-chip microcomputers to achieve this, using gate circuits and triggers to extract the second synchronization signal from the coded signal, and using a single-chip microcomputer to decode the time information. This method is still in use, but it has many components, complex structure, poor reliability, low synchronization accuracy, poor versatility, and is not conducive to functional expansion.

In order to solve the above problems, in this design, CPLD chip is used to realize the decoding of IRIG-B code, and the one used is EPM3256 of Altera. The simulation software used is MAX+PLUSⅡ, which can edit schematic diagram and VHDL language, and supports the mixed design of these editing methods. In this design, VHDL language is used to design the bottom module, and schematic diagram is used to design the upper module. The software has gate-level simulation function, can perform functional and timing simulation, and supports online download of target program.

The external IRIG-B coded signal is a differential signal transmitted at RS485 level and needs to be converted to TTL signal. The conversion chip is ADM2483 from AD Company. This chip is an enhanced RS485 transceiver with isolation and has functions such as failure protection, short-circuit current limiting, thermal shutdown and recovery. The external 5 MHz signal comes from a 5 MHz active crystal oscillator. The hardware block diagram is shown in Figure 2.

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3 Software Design of IRIG-B Code Decoding Module

3.1 IRIG-B Code Principle

IRIG (Inter Range Instrumentation Group) code is a time standard developed by the US Range Command Committee. There are 4 parallel binary time code formats and 6 serial binary time code formats. The most commonly used one is the IRIG-B time code format. B code can be divided into direct current (DC) code and alternating current (AC) code. The AC code is formed by amplitude modulation of the DC code with a 1 kHz sine wave carrier frequency; the DC code adopts pulse width coding. One frame per second contains 100 code elements, and the width of each code element is 10ms. There are 3 types of code elements. The pulse width of the position identifier is 8ms (position identifier P0~P9 and reference mark Pr), and the pulse widths of binary "1" and "0" are 5 ms and 2ms respectively.

Each frame starts from the reference mark Pr, that is, the leading edge of the second 8 ms pulse in two consecutive 8 ms pulses, which are Pr, 0th, 1st, ..., 99th code elements. Between Pr and P5 is the BCD field, which transmits the time information in BCD code format (including 4 types of information: seconds, minutes, hours, and days), with the low digit in front and the high digit in the back; the unit digit is in the front and the ten digits in the back. Between P5 and P8 is the CF field, which realizes the control function. The usage method can be formulated according to the protocol in actual use. This field is not used here. Between P5 and P8 is the SBS field, which is the time information in seconds (s) expressed in binary. The format of the IRIG-B code is shown in Figure 3.

3.2 IRIG-B code decoding scheme

The functional block diagram of the IRIC-B code decoder is shown in Figure 4.

1) Frequency division circuit The function of this module is to divide the 5 MHz clock signal and output 1 000 Hz and 9 600 Hz signals to provide a time reference for the symbol detection and recognition unit, the symbol recording unit and the asynchronous transmission unit. Multiple frequency divisions are performed to reduce the number of bits in the counter.

2) The code element detection and identification unit first performs serial-to-parallel conversion on the B code signal. 10 D flip-flops are connected in series, and a 1,000 Hz clock signal is used as their clock. In this way, the input data is output only when the rising edge of the 1,000 Hz clock signal comes, and the original output remains unchanged at other times. The output of the serial flip-flop is connected to 10 parallel D flip-flops respectively, and the output Q9~Q0 of the parallel D flip-flops is controlled by the rising edge of the IRIG-B code. When the output "Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0" of the parallel D flip-flop is "0011111111", the corresponding code element information is the identification bit; similarly, "0000011111" corresponds to the code element "1", and "0000000011" corresponds to the code element "0". The code element detection principle block diagram is shown in Figure 5.

3) Generation of the second synchronization pulse According to the result of code element recognition, if two identification bits are detected continuously, the second identification bit is the reference mark Pr, and its leading edge is the starting point of the second synchronization pulse. The first rising edge after the reference mark Pr corresponds to the moment when the second synchronization pulse is delayed by 10ms, so the second synchronization pulse signal should be generated by delaying 990ms at the moment corresponding to the first rising edge after the reference mark Pr, and the counter A recording the code element position information should be cleared when the second pulse is generated.

4) Codeword Recording Unit The codeword recording unit generates time information based on the codeword recognition result and the codeword position, including 7-bit second information, 7-bit minute information and 6-bit hour information.

5) Information Processing Because the current decoded time is the time information of the previous second, the information processing unit needs to add 1 second to the decoded time, and at the same time, in order to facilitate the subsequent transmission and processing of time information, the time information needs to be converted into BCD code format.

6) Asynchronous serial transmission The asynchronous serial transmission module sends the processed time information through the asynchronous serial port at a rate of 9,600 bit/s, 8 data bits, no parity bit, and 1 stop bit.

4 Conclusion

IRIC-B code timing is helpful to simplify circuit design and can reliably provide accurate time information. It will be increasingly widely used in power systems.

Traditional IRIG-B code decoders are mostly implemented using single-chip microcomputers, which have many components and complex structures. They may also freeze when subjected to external interference. The decoder designed with CPLD can greatly reduce the number of components, increase the stability of the decoder and the flexibility of application. The decoder module designed according to this solution is suitable for protection devices of various voltage levels, with reliable and stable performance, accurate time information, and high timing pulse accuracy (error is several μs).